Service manual

Service Manual
Cycling reset
You can find certain faults (such as address, data bus,
or ROM faults) more easily by constantly cycling the
reset line to the processor. This causes it to execute the
first few instructions in the ROM repetitively. One way to
do this is described in the section entitled Using the
external diagnostic interface on page 5-9. However, you
can instead use a fixed-rate oscillator that is built into the
reset circuitry. This oscillator will operate if you fit a
shorting link to LK5 on the main board, and will permit
the processor to run for about 500µS before being reset
for about 200µs.
Using the display adapter
The display adapter (Acorn part number 0086,804)
consists of a single-line 16 character liquid crystal
display with a few support components. See Fig 5-3: The
display adaptor. The integral test software uses this to
display textual progress and status messages. This has
the advantage that very little of the target machine's
circuitry need be running in order to display these
diagnostic messages – this is in contrast to the use of
the video display, which requires a great deal of the
machine to be working.
The display adapter has the following features:
• Reset button causes the POST sequence to
start (you can use this to interrupt
a POST that is running, and start
again)
• Pause button pressing this suspends the
operation of the POST, and
allows you time to note down the
displayed results of a particular
test
• 9-way D-type connector for the interface cable
socket
• 20-pin IDC socket used to connect the adapter to the
user port on the host machine.
You will find this connector, and
its cable, in a compartment on
the rear of the adapter.
To use the test adapter, proceed as follows:
1 Take the top cover off the machine, as described in the
section entitled Removing the top cover on page 3-1.
2 Plug the 9-pin DIN plug on the end of the interface
cable into the 9-pin DIN socket on the display adapter.
3 Plug the 6-pin connector on the other end of the
interface cable onto the external test connector LK4.
Note that the brown wire of the interface cable
corresponds to pin 1 on LK4.
4 Switch on the computer and press the Reset button on
the display adaptor to start the POST.
The computer will now cycle through the POST, and you
can follow the progress of the test on the LCD. If you
need to make a note of any results as the tests are
progressing, press the Pause button. This will temporarily
suspend the POST, and retain the current message on
the display.
If you want to run the POST again, press the Reset
button on the adapter.
Each test is preceded by a display of the form
ROM:
where the colon indicates that the test has been started.
If the test is passed, no further message relating to that
test is displayed. If a test fails, then a message of the
form
ROM bad 124AF007
is displayed, where the message indicates the nature of
the fault in a context-dependant manner.
Some tests complete by displaying a status message
which is neither a pass nor a fail, but for information only (
or for the operator to determine the result). These are of
the form
M Size 4000.20
where the information is again dependant on the context.
A short delay occurs after every message to give you
time to read it: you can extend this by operating the
Pause button, which suspends further output until you
release it. The test then proceeds normally.
Messages with a numerical content (except for the
display of the software release number) are always
displayed as one or more hexadecimal fields.
Note that these tests are the same as those performed by
the POST. The only difference between the test
sequences are that the POST skips the message display
when it is found not to exist, and the use of the display
adapter avoids the test of an 10C register to determine
the necessity for a test sequence. Hence, IOC faults
which cause the test sequence to hang in a very early
phase are not a problem.
The messages shown on the display adapter are
explained below.
Sign on
The first message displayed occurs immediately after the
display interface is detected. It consists of a sign-on
message indicating the release level of the test software
in ROM:
SELFTEST R1.13
After this, VIDC is initialised for a mode 0, sync 0 monitor
and the purple screen colour is set, as in the POST.
ROM checksum
The ROM checksum test is preceded by the message
ROM:
and consists of a simple 32-bit wide additive checksum of
every word in ROM except the last 2 (ie from &3800000
to &387FFF8 for 1 MBit ROMs). The last two words are
5-4 Issue 2, June 1991 Part 5 - Main PCB fault diagnosis