Service manual

Service Manual
HCT273), which are directly connected to the EPROM,
but isolated from the SRAMs by IC3 (HCT541). The
EPROM (IC5) and the ISR (IC15, PAL 0273,215) also
have an 8 bit data bus buffer (IC2 HC245) separate from
that used for the SRAMs, DMAC and SBIC. Again, this
allows ARM access independent of DMA activity. IC4 (
HC245) and 106 (HC245) provide 16 bits of data bus
buffering for the SRAMs (IC13 and IC11), as well as the
DMAC and SBIC. IC7 (HCT573) is used to hold the
upper 8 address bits for the DMAC during DMA transfers,
and IC8 (HC245) routes the data to the correct SRAM,
depending on the state of A0. The DMAC 'sees' the
SRAM as 64K by 8 bits, whereas the ARM 'sees' the
SRAM as 32K by 16 bits. IC17 (uPD71071) is the DMAC
and 1016 (WD33C93A) is the SBIC.
All address decoding is taken care of by IC9 (PAL 0273,
216). The task of arbitration for access to the SRAM is
shared by IC15 (PAL 0273,215) and IC14 (PAL 0273,
217), 1018 (PAL 0273,219), and IC12 (PAL 0273,218).
IC14 also generates the IOGT and BL signals required by
the podule Bus, while IC12 handles the I/O and memory
read and write lines (IORD, IOWR, MEMR, MEMW).
There are various link options on the SEC and they are
listed below:
Issue 2+ expansion card:
EPROM size select
EPROM
LK1
LK2
LK3
LK4
LK5
LK7
27128
C
0
0
0
C
C
27256
0
0
0
C
C
C
27512
0
C
0
C
0
C
27C101
0
C
C
C
0
0
0- Open
C - Closed
Factory fitted links set the size of the Issue 2+ PCB to
27256.
LK8 and LK9 allow for larger SRAM devices, but these
could not be fully addressed by the ARM processor.
LK10 and LK6 switch the reset line for initiator or target
mode:
Mode
LK10
LK11
Initiator
target
O
C
C
O
The PCB is factory configured for initiator mode.
The SCSI bus signals are connected from the SCSI bus
connector to the SBIC, via filter capacitors clearly visible
on the circuit board. The SCSI bus requires termination at
each end of the bus cable on all signal lines. These are
220R to +5 volts and 330R to 0 volts. Where no internal
drive is fitted, termination is provided internally by a plug-
on terminator PCB assembly, which is mechanically
polarised. Power to these termination resistors is
provided via diode D1, to allow target devices on the SCSI
bus to power them should the initiator be switched off. The
initiator may also power the terminators at the far end of the
SCSI bus cable. Fuse FS1 limits the current to a maximum
of 1 Amp. TR1 provides an open-collector drive to the
SCSI reset signal when the SEC is used in initiator mode.
The SCSI expansion card state machine
This section describes the difference between a SCSI 1
state machine and a SCSI 2+ state machine. For a full
description of the SCSI 1 state machine, see the SCSI
Expansion Card Service Manual.
When the ARM system memory clock is run at a different
speed from that of the I/O clock, a period of
synchronization (minimum 1 I/O clock cycle) is required at
the beginning and end of each I/O cycle. These extra
clock cycles cause the earlier SEC design to relinquish
and re-arbitrate for SRAM access on every register
transfer of an STM or LDM command, degrading
potential performance. The solution to this was to cause
the Issue 2+ state machine to hold access to the SRAM
for the ARM for a number of clock cycles after the
completion of the I/O cycle. This allows for
synchronisation clock cycles and will, conveniently, span
video DMA interruptions too. This is achieved by the use of
a three bit counter built in to the PAL 0273,218 and count
decode logic in the new PAL 0273,219. Figure 2-13 shows
two accesses to the SBIC. The first access is a write to
the address register in order to pre-select a register. The
second is a register read. Note that because LA13 is high
the second access is an E-cycle, even though the ARM
has control. Figure 2-14 shows an LDM from SRAM. Note
that LA13 is low throughout this command. When the
extended cycle is complete the RW_DN signal is
activated and the counter starts to count from zero
again. However, each time an IORQ is received, it is reset
to zero. Hence we see the counter oscillating between
zero and one until the end of the LDM, when it counts
out to seven, and the bus control is relinquished. Figure 2-
15 shows an STM split up by video DMA accesses and the
counter reaching a higher count before being reset to
zero.
2-20 Issue 2, June 1991 Part 2 - Interface cards