Service manual

Service Manual
The final section of the podule hardware is the interrupt
control logic. There are two sources of interrupts within
the SEC, the DMAC and the SBIC. The DMAC will issue
a terminal count (TC) pulse at the end of a data transfer
which will be latched by the ISR, and may be
subsequently read at any time by the ARM processor.
SBIC interrupts are latched within the SBIC, but can be
monitored in the ISR. DMAC interrupts remain latched
until the Clear Interrupt (CLRINT) address is written to.
SBIC interrupts remain latched until appropriate action is
taken by the host. The two interrupt sources are
combined in a PAL to form a common PIRO.
The address map for podule slot 0 fast access is given
below:
Bit
MPR Bit Allocation
ISR Bit Allocation
7
1 = User Reset
X Not used
6
1 = Interrupts Enabled
X Not used
5
EPROM Pa9e Address
X Not used
4
EPROM/SRAM Page Address
X Not used
3
EPROM/SRAM Page Address
1 = SBIC Interrupt
2
EPROM/SRAM Page Address
X Not Used
1
EPROM/SRAM Page Address
1 = DMAC Terminal
Count Interrupt
0
EPROM/SRAM Page Address
1 = SEC Requesting IRQ
In Module address space the ARM has access to the
SRAM via a 16 bit data bus and addresses it as 16 4KB
pages (8K addresses 16 bits wide, every 4th address),
using the MPR located in podule address space.
LA2 of the podule bus is connected to A0 of the SRAM,
so that the lower 16 bits of the ARM registers will be
stored in consecutive addresses when an STM
instruction is used.
The DMAC and the SBIC are also memory mapped but
only have 8 bit data buses. The DMAC has many
registers which are normally accessed using address bits
AO through A7 of the host processor address bus. Due to
the funnelling required to exchange data between 8 bit
and 16 bit data buses, the DMAC addressing has had to
be mapped rather unusually. Al through A7 on the DMAC
are connected to LA2 through LA8, and AO on the DMAC
is connected to LA9.
Thus the mapping becomes:
Normal Offset
SEC Offset
Register
0000
0000
Initialise
0001
0200
Select Channel to Program
0002
0004
Transfer Count Low
0003
0204
Transfer Count High
0004
0008
Transfer Address Low
0005
0208
Transfer Address Mid
0006
000C
Transfer Address High
0007
Unused
0008
0010
Device Control Register 1
0009
0210
Device Control Register 2
000A
0014
Mode Control Register
0008
0214
Status Register
000C
0018
Temporary Register Low
0000
0218
Temporary Register High
000E
001C
Request Register
000F
021C
Mask Register
The SBIC is used in the indirect addressing mode where
LA2 is used as AO to select between control registers
and the address register (see data sheet).
When a DMA transfer between SBIC and SRAM is in
progress, the ARM may still access the DMAC, SBIC or
SRAM in the normal manner simply by reading or writing
to the appropriate address. All arbitration required to gain
access to the SEC internal buses is carried out
transparently by stretching the MEMC I/O cycle (see the
podule bus specification). In the case of an STM and
LDM instruction only the first access is stretched to gain
control of the SEC buses. The ARM will normally retain
control of the SEC buses during video DMA interruptions.
Module Address Map:
SRAM paging is exactly the same as EPROM paging.
Component identification on the SEC
EPROM address lines from the ARM podule bus are
unbuffered. This allows them to operate during DMA. The
extra address lines are provided by the MPR (IC1
Part 2 - Interface cards Issue 2, June 1991 2-19