Service manual

Service Manual
SCSI interface
Overview
Workstation models which provide a SCSI interface do
so by means of a SCSI expansion card (Podule) plugged
into an expansion slot in the backplane.
The Small Computer System Interface (SCSI) is a high-
speed interface for use mainly with mass storage
devices such as hard discs, tape drives or CDs. It is an
asynchronous bus capable of data transfer rates up to
4MB per second. The bus cable is a 50 way cable
consisting of:
• 30 Ground wires
• 9 Control signals
• 8 Data signals
• 1 Data parity signal
• 1 Terminator power line
• 1 Not Connected.
The pin allocation for the two standard SCSI bus
connectors can been seen on the schematic.
Communication on the bus is between two devices, an
initiator and a target. In the most common case the
initiator will be the host computer and the target will be a
hard disc drive. The first task for the initiator is to select
the required target. There can be up to eight devices on
a single SCSI bus, each having its own unique select
code.
This select code is simply a different single bit of the
data bus allocated to each device on the SCSI bus.
Generally the host computer uses select code seven (
data bit 7) and the first target will use select code zero (
data bit 0).
Having selected its target, the host then transfers a small
group of bytes known as the Command Descriptor Block
(CDB) to the target. The CDB defines the action to be
taken by the target. In the case of a disc drive this will
usually be to send some data to the host, or to receive
some data from the host and write it onto disc.
The SCSI bus will go through many 'Phases' during the
execution of such a command and the target may even
release the bus (or 'Disconnect') during the execution of
a command (for example if a 'Seek' is required by a hard
disc drive), thus allowing the host (or initiator) to initiate
commands on other targets.
The complexities of SCSI Bus Phases, handling target
disconnections etc, can be all taken care of by single
chip SCSI controllers.
For further details of the functions of the SCSI bus, refer
to the ANSI Standard X3.131-1986 and the data sheet
for the SCSI controller used in the Acorn SCSI
expansion card (see the section entitled Bibliography on
page 2-23).
Circuit description of the SCSI
expansion card (Issue 2+)
Maximum performance is achieved from the Acorn
expansion bus by the use of the STM (STore Multiple)
and LDM (LoaD Multiple) ARM assembler instructions to
transfer data to and from a peripheral device. These
instructions, coupled with the full use of the 16 bit I/O
data bus, will provide a maximum data transfer rate of 8
MB per second. Unfortunately these commands cannot
be used to transfer data to and from the SCSI controller
chip directly, because it cannot be predicted whether or
not the WD33C93A (the device used in this design) can
accept or provide the mandatory number of bytes for the
relevant instruction.
Furthermore, the WD33C93A is an 8 bit device, hence
some kind of funnel hardware is required to couple the 8
bit bus to the 16 bit I/O bus.
The solution to these problems is to have buffer memory
on the expansion card, accessible by both the
WD33C93A and the ARM processor. This dual porting of
the buffer memory is the most complex aspect of the
circuit and is therefore dealt with separately.
The main elements of the SCSI Expansion card are:-
• Western Digital WD33C93A SCSI Bus Controller
• NEC 71071 DMA Controller
• two 32K by 8 bit Static RAMs
• EPROM containing the driver software
• five PAL devices controlling ARM access to the card
• SCSI bus connector, termination resistor packs, and
filters
• data and address bus buffers and latches.
The SCSI Expansion Card (SEC) has hardware in both
Podule (expansion card) I/O space and Module I/O
space. The podule section consists of the ID/RISC_OS
driver EPROM, the interrupt status register and the
EPROM page register. This page register is also used for
the SRAM (Static RAM buffer memory) page. The podule
hardware is kept isolated from the Module hardware to
allow accesses to the Interrupt Status Register (ISR) and
the Memory Page Register (MPR) not to interfere with
any DMA process that may be taking place between the
SCSI Bus Interface Controller (SBIC) and the SRAM.
The EPROM circuit permits from 8 KB up to 128 KB of
code space, the top two bits of the MPR being used for
interrupt enable (IE) and user reset (UR). The IE is 0 by
default and has to be set to 1 before any interrupts can
be generated by the SEC. The UR bit is also 0 by default
and if set to 1 will cause the internal reset line (IRST) in
the SEC to become active. The DMAC has a minimum
reset period of 2tCYK (250ns) and the SBIC has a
minimum reset period of 1µs. The MPR is not cleared by
the IRST signal. A link option does allow the SCSI bus
reset to control the IRST, should the card be required to
act as a target. The SBIC will inform the host processor
that a reset has occurred.
2-18 Issue 2, June 1991 Part 2 - Interface cards