Service manual

Service Manual
Local Buffer Memory
The buffer memory consists of two 8k x 8 (up to 512k x 8
for SRAM source flexibility) static RAMs which give a 16
bit data transfer across the podule interface, hence
maximizing the podule bandwidth. The data buffer is
completely controlled by the NIC controller, which
performs all the memory management in a ring buffer
format. Pointers to the memory are updated as required (
but can be accessed via the NIC registers if necessary).
The data buffer is transparent as far as data transfers
across the podule interface are concerned.
NIC Controller
The National Semiconductor Network Interface Controller
provides all the functions necessary to implement all
Media Access Control (MAC) layer functions for
transmission and reception of packets in accordance with
the IEEE 802.3 standard. All bus arbitration and memory
support logic and two DMA channels are integrated into
the NIC. The local DMA channel transfers data between
the internal controller FIFO and local memory. On
transmission, the packet is transferred from local memory
to the FIFO in bursts. Should a collision occur, the packet
is re-transmitted with no processor intervention. On
reception, packets are transferred from the FIFO to the
receive buffer ring. A remote DMA channel is provided to
transfer between local buffer memory and system
memory. Full details for operating the NIC are contained
in the data book (see the section entitled Bibliography on
page 2-17).
IEEE802.3 Interface Components
These are the components concerned with the
Ethernet/Thin-wire Ethernet interface. They include the
20MHz oscillator (providing the required transmit and
receive clock), the Manchester encoder/decoder, DP8391
(to produce the required signals), the transceiver/line
drivers,DP8392 (required to provide thin-wire Ethernet
signals) and components to provide isolation such as the
DC to DC convertor, line transformers, termination
resistors, capacitors and a diode as required.
PALs
There are four PALs used:
• Decode
• Intbuf
• Memcpal
• Natfix.
Decode (0273,271)
As its name suggests, this PAL decodes podule and
module addresses to produce chip select signals. It
enables reading of the EPROM, writing to the page
register, reading interrupt status, and read/write
operations to the NIC controller main podule interface
functions. It also defines whether podule or DMAC have
control of the bus. The PAL's function is shown by the
state flow diagram below.
Intbuf (0273,272)
The 'intbuf' PAL, in conjunction with the 'memcpal' PAL,
form the core to the Ethernet podule bus arbitration
logic. Intbuf produces the interrupt control and all the
functions required to control the I/O Port (HCT646s,
which are used in both latched and transparent mode,
depending on the type of access active).
Memcpal (0273,273)
The 'memcpal' PAL, working in conjunction with the '
intbuf' PAL, produces all the podule interface (MEMC)
required read and write pulses. The Ethernet controller
has two main modes of operation – Bus Master (while
performing DMA) and Bus Slave (while its internal
registers are being accessed. These two modes require
two different types of access cycle (a different bus
arbitration is used). Within these two modes a read or a
write cycle may be in operation. The PAL's function is
shown by the state diagram overleaf
The internal reset will set this PAL to the 'Idle' state. It
remains in this state until a MEMC cycle is decoded.
From the 'Idle' state it may enter one of four states:
• Slave Read
• Slave Write
• Master Read
• Master Write.
On entry to one of these states, a complete cycle will
follow. Whichever state it has entered, it will remain in
that state while the bus arbitration function is completed.
Once access has been granted, the cycle continues,
producing read or write pulses and MEMC signals (
including waiting during interrupts) as required.
Natfix (0273,274)
The National Semiconductor NIC Ethernet controller
requires care to be taken when trying to access its
internal registers via the control signal Chip Select. The
PAL Natfix is used to monitor the controller's use of the
bus and then hold back any access to the registers while
the controller is using the bus. It similarly holds back the
controller during a register access, and has the effect of
making sure that Chip Select doesn't become active on
a rising edge of the 20MHz clock.
2-16 Issue 2, June 1991 Part 2 - Interface cards