Service manual

Service Manual
Circuit component details
Decode and cycle access control
The Ethernet II expansion card has hardware in both
podule space and Module space. The podule section
consists of the ID/RISC OS driver EPROM, the interrupt
status register and the EPROM page register. The podule
hardware is kept isolated from the Module hardware so
that accesses to the Interrupt Status Register and Page
Register do not affect any DMA transfers in progress on
the Ethernet podule internal bus.
The podule memory map is shown below:
Address PO
LA13
LAl2 use
03343000
1
1 WRITE Page Register
READ not defined
03342000
1
0 WRITE not defined
READ Interrupt status
03341000
0
1 SRAM test
03340000
0
0 EPROM (Paged)
The Interrupt Status register is as follows:
bit7
=
X
Not used
bit6
=
X
Not used
bit5
=
X
Not used
bit4
=
X
Not used
bit3
=
X
Not used
bit2
=
X
Not used
bit1
=
X
Not used
bit0
=
interrupt pending
When the Ethernet II expansion card generates an
interrupt, the 'podule manager' will interrogate the status
register (as defined by the podule ID) to check for bit 0 set
active low.
In Module space the ARM has access to the Ethernet
controller and the data transfer I/O Port. When a local
DMA transfer between NIC and SRAM is in progress, the
ARM may still access the NIC or I/O Port in the normal
manner, simply by reading and writing to them. All
arbitration required to gain access to the Ethernet II
expansion card internal bus (when accessing the NIC) or
waiting for data to be ready at the port, is carried out
transparently by stretching the MEMC cycle.
The NIC has 46 registers (normally accessed using
address bits RAO through RA3 of the host processors
data bus. RAO through RA3 on the NIC are connected to
LA2 through LA5) which provide the flexibility and
programmability to handle both the Ethernet interface and
also the interface to the local memory and controlling
processor.
The I/O Port is used to transfer packets of data to and
from the Ethernet/thin-wire Ethernet via the podule
interface, by simply writing or reading the required data
file length in 16 bit wide words. The individual bytes being
transferred automatically between the Port and Network
via the NIC and SRAM.
The Module memory map address is shown below:
Address PO
LA13
LA12 use
03003000
1
1 MC controller
using LA5—LA2
03002000
1
0 Data transfer I/O Port
Podule and Ethernet identification
The ID/RISC OS driver PROM has been laid out to give
from 8kB to 512kB of code space. The host cannot directly
address the full PROM and therefore is operated in a page
mode by writing the required page to the page register.
The page register is set for page zero by power on reset.
The top two bits of the page register being used for 'Lr_w' (
access to the I/O Port is set for reading or writing a
packet) and 'Srst' (software internal reset). The page
register is not cleared by the 'software internal reset'.
The page register is as follows:
bit15
bit14
=
=
Srst (active low)
Lr_w (active high — read)
bit13
=
bit12
=
bit11
=
bit10
=
bit9
=
bit8
=
EPROM page address bit 8
bit7
=
EPROM page address bit7
bit6
=
EPROM page address bit 6
bit5
=
EPROM page address bit 5
bit4
=
EPROM page address bit 4
bit3
=
EPROM page address bit 3
bit2
=
EPROM page address bit 2
bit1
=
EPROM page address bit 1
bit0
=
EPROM page address bit 0
Part 2 - Interface cards Issue 2, June 1991 2-15