Service manual

Service Manual
interrupt location, the Ethernet ID of the particular
board (each PROM is programmed with a different
number) and required driver code to run under RISC
OS. It is page addressed by writing to 'mode' latch.
System reset sets to page zero.
3 Data Buffer:
Static RAM memory. Memory access is completely
controlled by the NIC controller which performs the
memory management. Data is transferred between
the controller and SRAM using local DMA, and
between the SRAM and the PORT by remote DMA.
4 NIC controller:
Provides the required data rate with a minimum of
control overhead. This is a key element in the design.
Once set up it performs many of the Ethernet
functions without requiring processor help, only
producing an interrupt when a packet has been
completely received or transmitted.
5 IEEE802.3 Interface Components:
Providing the Manchester encoding/decoding, high
voltage isolation and line drivers for the thin-wire
Ethernet interface.
Fig 2-11: Ethernet II block diagram
2-14 Issue 2, June 1991 Part 2 - Interface cards