Service manual

Service Manual
Ethernet II expansion card
The IEEE 803.2 standard supports two different
versions for the media:
• 10BASE5 (commonly known as Ethernet)
• 10BASE2 (thin-wire Ethernet, or 'Cheapernet'). These
can be used-separately, or together in a hybrid form.
Both versions have similar electrical specifications and
can be implemented using the same transceiver chip.
Thin-wire Ethernet is the lower cost version and is user-
installable. Main differences are in the segment length,
network span and nodes per segment, with thin-wire
Ethernet having only one-third of the performance. The
capacitance per node and the cable cost are however
much less.
The Ethernet expansion card has been designed to
provide the physical and media access control layer
functions of the local area network as specified in IEEE
802.3 standard. This standard is based on the access
method known as Carrier-Sense Multiple Access with
Collision Detection (CSMA/CD). In this scheme, if a
network station wants to transmit, it first 'listens' to the
medium; if someone else is transmitting, the station
defers until the medium is clear before it begins to
transmit. However, two or more stations could still begin
transmitting at the same time and give rise to a collision.
When this happens, the two nodes detect this condition
and back off for a random amount of time before making
another attempt.
System considerations
Bus Latency is the maximum time between the NIC (
Network Interface Controller) assertion of BREQ and the
system granting BACK. This is of importance because
of the finite size of the NIC's FIFO. If the bus latency
becomes too great, the FIFO overflows during
reception, and becomes empty during transmission. The
Bus Utilization is a fraction of the time the NIC is the
master of the Ethernet podule internal bus, and this
should be minimised. The lowest bus utilization occurs
when the bursts of data across the podule interface are
as long as possible. This requires the threshold as high
as possible, and Empty/Fill mode is used. The
determination of the threshold is related to the maximum
bus latency the system can guarantee.
A DMA set up and recovery time is associated with each
burst, hence when longer bursts are used, less bus
bandwidth is required to complete the same packet.
Hardware overview
The Ethernet II expansion card has been designed
around the National Semiconductor Chip Set. This
provides all the functions necessary to implement an
IEEE 802.3 (Ethernet/thin-wire Ethernet) interface on a
host computer or a peripheral device. As there is no
direct DMA memory path across the podule bus, data is
transferred via a static RAM local buffer. Since both the
ARM and the DMAC will have access to the Ethernet II
expansion card internal bus, some arbitration is
required.
Dual-port memory equivalent
This configuration makes use of the NIC's remote DMA
capabilities, and requires only a local buffer memory
and a bi-directional I/O port. The high priority network
bandwidth is decoupled from the system bus, and the
system interacts with the local buffer memory using a
lower-priority bi-directional I/O port. When a packet is
received, the local DMA channel transfers it into the
buffer memory, part of which has been configured as
the receive buffer ring. The remote DMA channel
transfers the packet on a byte by byte basis to the I/O
port. At this point the data is transferred through an
asynchronous protocol into main memory.
Remote DMA
The remote DMA channels work in both directions;
pending transmission packets are transferred into the
local buffer memory, and received packets are
transferred out of the local buffer memory. Transfers
into the network memory are known as remote write
operations, and transfers out of the local buffer memory
are known as remote read operations. A special remote
read operation, Send Packet, automatically removes the
next packet from the receive buffer ring. Both the
starting address and the length are set before initiating
the remote DMA operation. The remote DMA operation
begins by setting the appropriate bits in the Command
Register. When the remote DMA operation is complete,
the RDC bit in the Interrupt Status Register (ISR) is set
and the processor receives an interrupt. When the Send
Packet command is used, the controller automatically
loads the starting address and byte count from the
receive buffer ring for the remote read operation. Upon
completion it updates the boundary pointer for the
receive buffer ring. Only one remote DMA operation can
be active at any time.
Hardware components
The Ethernet II expansion card can be divided into five
major blocks (see Fig 2-11: Ethernet II block diagram).
The five major blocks are as follows:
1 Decode and cycle access control:
Carrying out address and register decoding, control
of the local buffer (latched or transparent mode) and
all the required read/write signals. The type of
access cycle required may be extended if bus
arbitration is needed.
2 Podule and Ethernet identification:
A PROM containing the ID of the type of podule (
expansion card) that is fitted, with the address of the
Part 2 - Interface cards Issue 2, June 1991 2-13