Service manual

Service Manual
PS* while the LANCE is idle
If the LANCE remains idle while the podule bus cycle
occurs then there is no collision and the LANCE ignores
the READY signal. This case is not illustrated.
A read from the podule ID PROM or write to the control
or page register is similar to a RAM cycle. To simplify
the bus design the LANCE is removed from the RAM
buses during cycles to these devices.
Bus design note
The cycle stealing scheme should guarantee that the
LANCE never has insufficient bus bandwidth or sees
excessive bus latency to the extent that it cannot service
the net or fails to meet the IEEE timings. Even when the
ARM continuously accesses the RAM. The following
gives the reasoning behind this statement: Assumptions:
Net Clock 10 MHz
Bus Clock 8 MHz
LANCE FIFO size 16 bytes
HOLDA is wired to HOLD so:
Bus Latency 0 cycles
IEEE Interframe Space Time = 9.6 µS
Criteria:
1 FIFO must not over/underrun.
FIFO fill/empty time from serial side:
= 8 (bits)* 16 (bytes) " 100E-9 (bit time) =
12.8 µs
FIFO empty/fill time from parallel side:
= 8 (Word transfers)
* (4 (standard 8 MHz cycles) + Nwait (wait
cycles))
* 125E-9
= 4 µs (if Nwait = 0)
= 7 µs (if Nwait = 3)
= 8 µs (if Nwait = 4)
2 The LANCE must be in a position to transmit by the
end of the interframe spacing time.
With a Fp/Fs ratio of 8 MHz/10 MHz (0.8):
16*Nwait + Nlatency must be less than or equal
to 80.
If HOLDA = HOLD then Nlatency 0
and
Nwait <= 5
So this strategy works if we can keep the number of wait
states (Nwait) less than or equal to five per access. In
the current design three are used and this is unlikely to
change.
Interrupts
The podule interrupt (PIRQ) is level triggered. However,
the interrupt signal (INT) from the LANCE is designed
for use with edge triggered interrupt controllers. If the
net controller detects a second interrupting condition just
after the first is raised, it will drop and reassert INT. The
situation could arise where the podule manager (
software) may scan the slots and find no IRQ flag set.
The above problem is prevented by latching INT in the
interrupt and channel attention PAL (IC78) and using the
latched signal INTO to generate the flag. The clear
interrupt (CLI) bit in the control register is used to clear
the latch.
Latching INT introduces another problem, which is
eliminated by a feature of the 82586 LANCE. If a second
interrupt occurs after the processor has read the status
word in the SCB, but before the first is cleared, then the
second interrupt would be missed. However, if the
interrupt is cleared at the same time as the channel
attention (signalling the acknowledge command) is
issued, the LANCE will respond by deasserting INT and
reasserting if the second interrupt was not
acknowledged because it was missed. It is
recommended to set CA whenever CLI is set.
Figure 2-8: Example interrupt cycles
2-10 Issue 2, June 1991 Part 2 - Interface cards