Service manual

Service Manual
The state machine and operation
The state machine has four states; IDLE, SA1, SA2, and
SA3 and is clocked from state to state on the falling edge
of CLK8, the 8 MHz podule bus clock. See Figure 2-2:
State diagram.
The idle state
The state machine enters this state on power-up, hard
reset (RST* low), or from the SA3 state. In this state the
bus buffers on the ARM side of the dual-ported RAM are
disabled and those on the LANCE side enabled. Other
outputs such as the page and control register bits remain
unchanged. The state machine remains in the idle state
until the ARM starts an access (podule select - PS
active).
The SA1 state
This state is entered from the idle state only. In this state
the LANCE READY signal is disabled, forcing the
LANCE to insert wait states if it is active on the bus. The
RAM write strobe (RAMWE*) is disabled to prevent
writes while the LANCE side of the dual-port RAM is
disabled and the ARM side enabled. The state machine
exits to the SA2 state unless a reset occurs.
The SA2 state
This state is entered from the SA1 state only. In this
state the ARM access is performed and the
corresponding device enables are active eg, if a RAM
write is performed then the RAM write strobe (RAMWE*)
is active. Similarly if a RAM or ID read is required than
the RAM or IDOE is active. Writes to the page register or
control bits are also
performed during this state. READY is still inactive. The
state machine exits to the SA3 state unless a reset
occurs.
The SA3 state
This state is entered from the SA2 state only. The RAM
write strobe (RAMWE*) is disabled to prevent writes
while the LANCE side of the dual-port RAM is enabled
and the ARM side disabled. The state machine exits to
the idle state where any LANCE access that was in
progress is completed.
Podule bus cycles
The podule specification requires all ID PROM access to
be made using type 3 (sync) IOC bus cycles. All other
accesses to the Ethernet podule must be made using
type 2 (fast) IOC cycles.
Figure 2-3: Typical podule bus cycle illustrates a
read/write to RAM while the net controller is active. The
cycle starts with podule select (PS) active and puts the
state machine into the SA1 state on the next clock edge.
A description of each state that follows is given above.
It should be noted that Ready is always deasserted for
three cycles, even if the LANCE is idle. A podule bus
access can 'collide' with a LANCE access in five different
ways, depending on what state the LANCE is in when
the podule bus access starts. These are: PS* while the
lance is in states T1 to T4 or idle. The actual number of
wait states that the LANCE will insert depends on which
of these cases apply. Figures 2-4, 2-5, 2-6 and 2-7
illustrate the possible cases.
Figure 2-2: State diagram
2-6 Issue 2, June 1991 Part 2 - Interface cards