Service manual
Service Manual
and the ARM has to correct the count. Error counts this
high indicate a major problem that will require correction
so should be a rare event.
The memory bus of the LANCE is operated in 'minimum
mode' as the timing parameters for LANCE outputs in
this mode are subject to less spread between devices.
The pull-up resistors on WR*, RD*, and BHE are
required to prevent RAM cycles when the LANCE is
inactive.
The LANCE communicates directly with the SIA (IC24)
via a serial channel comprising seven signals: TXC,
TXD, RXC, RXD, RTS, CRS and CDT. The function of
each of these is described in the LANCE data sheet. The
Clearto-Send (CTS*) input is not supported by the SIA
and is connected to 0V (enabled).
Dual port RAM
The podule bus provides only a limited space in the
address map (8 KB) for each podule. This is insufficient
and so a paged scheme has been implemented.
Viewed from the ARM side the RAMs are paged into the
top half of podule space by a 'page register'. The four bit
page register is split across two PALs (see the section
entitled The PALs). Sixteen pages each of 4 KB provide
64 KB in total. This is organised as 32 k x 16 bits (two 32
k x 8 static RAMs). An alternative RAM size of 8 k x 16
bits (two 8 k x 8 static RAMs) can be supported (see the
section entitled Links on page 2-12).
The podule address bus (LA2-13) is buffered by two
HCT244 (IC66 and IC58) and the podule data bus (BD0-
BD15) is buffered by and two HCT245 transceivers (
IC15 and IC54). The direction of the data bus
transceivers is determined by the podule R/W signal,
while both output enables (AAOE and BDOE) are
generated by the bus control PAL (IC36).
Viewed from the net controller side, the RAM will be
contiguous from location 0x0000 to 0xFFFF. The
initialisation root for the controller is 0x0FFFFF6 which is
mapped into the RAM at 0xFFF6. The high order
address bits are not decoded.
The LANCE address/data bus (AD0-AD15) is
demultiplexed by two HCT245 (IC17 and IC22) which
use the LANCE ALE signal to latch the address bus. The
data bus only requires buffers and two HCT573
transceivers (IC10 and IC32) are used. The direction of
the data bus transceivers is determined by the LANCE
DT/R signal, while the output enables are generated by
the bus control PAL (IC36).
The LANCE is capable of operating on an eight bit bus
and is reset to this mode. The LANCE initialisation root (
read when released from reset) contains a bit that
defines the bus width and this must be set to 0 (=16 bit
bus). Until the LANCE reads this it deasserts Byte High
Enable (BHE*) and outputs address bits on AD8-AD15
for the entire cycle. To avoid a bus clash BHE* is used to
disable the high order data bus transceiver via the bus
control PAL (IC36).
Once initialised to a byte wide bus the LANCE only
operates on half words (never bytes) so it not necessary
to decode the least significant address bit (ADO) to
produce separate write strobes for each byte.
Podule Identification PROM
The device used is a 32 byte PROM 27LS19 (IC14).
Typical content of an ID PROM is shown in Table 2
overleaf.
The ID PROM shares address and data bus buffers with
the RAM. Viewed from the ARM side the ID PROM is
byte wide and word aligned.
The podule specification defines two bits in the ID byte to
be interrupt flags. This design requires only IRQ
interrupts so the FIQ flag is always zero. The IRQ flag is
generated by connecting the podule interrupt signal to
the most significant address pin. The content of the
upper half is similar to the lower half but has the IRQ flag
bit set, in this way the interrupt flag is multiplexed 'into'
the ID byte.
Bytes 09 - 0E are the six byte Ethernet address unique
across all Ethernet equipment from manufacturers
worldwide.
The CRC (Bytes 1C - 1F) is calculated on the rest of the
PROM (Bytes 00 - 1B) using a 32 bit Autodin - II CRC
polynomial. This is the same algorithm as the LANCE
uses to perform multicast address filtering (see the
section entitled PROM CRC calculation on page 2-12).
Since each PROM is unique the CRC is used to perform
verification.
The output enable is generated by the bus control PAL (
IC36).
The PALs
Three PALs are used in this design:
• the main state PAL (IC29)
• the interrupt and channel attention PAL (IC78)
• the device enable control PAL (IC36).
The main state PAL (IC29)
This PAL implements a state machine which provides
timing information for the other two PALS in the design.
In addition it produces the two least significant bits of
both the page register (PRO and PR1) and control
register (RSTO and LOOP).
The interrupt and channel attention PAL (IC78)
This PAL implements the two most significant bits of
both the page register (PR2 and PR3) and control
register (CLI and CA).
The device enable control PAL (IC36).
This device decodes the address map to provide various
device output enables.
2-4 Issue 2, June 1991 Part 2 - Interface cards