Service manual

Service Manual
The LANCE
The 82586 LANCE is a 'scatter-gather' DMA controller
type device and is designed to interface to 80186 type
processors using a HOLD/HOLDA protocol to resolve
arbitration for access to shared memory.
The ARM podule bus cannot easily support a
HOLD/HOLDA type interface. This is because the ARM
is a dynamic device and cannot be stopped for the
required time. (This can be longer than 10µs during the
interframe/interpacket spacing time.) The ARM cannot
be given priority and HOLDA de-asserted because this
will result in the net controller failing to meet the timing
requirements of the net protocol due to the increased
bus latency. For example, this could result in the failure
of the net controller to take part in the back-off and retry
sequence following a collision on a heavily loaded net.
In this design HOLD and HOLDA are wired together and
ARM cycles cause wait-states to be inserted into the
LANCE bus cycle. This is achieved by removing the
READY signal to the LANCE while the ARM is active.
Adopting this scheme avoids the problems outlined
above. The ARM is never stopped and the LANCE sees
minimal bus latency.
The LANCE ARDY/SRDY input used can be
programmed to be either asynchronous/ ARDY and
internally synchronised, or synchronous/SRDY and
externally synchronised. In this case it is SRDY mode
that must be selected. This is achieved by issuing a
configure command with the ARDY/SRDY bit set to logic
1. This is important as the LANCE powers-up in ARDY
mode.
In certain circumstances the LANCE needs to perform
read-modify-write bus cycles with lockout. Using READY
to insert wait-states does not allow this. However lockout
is only required when the LANCE updates error counts (
statistics) and even then a problem only arises when a
count overflows and the ARM resets it to zero while the
LANCE is in the modify phase of a read-modify-write
cycle. This is solved by the ARM reading back the count
after it sets it to zero. If the count is still indicting an
overflow then a read modify-write cycle was in progress
Table 2-1: Ethernet I expansion card address map
ID PROM (Base) = Slot base (Type 3 access) + 0x0000 (Read only)
Page Register = Slot base (Type 2 access) + 0x0000 (Write only)
Control Register = Slot base (Type 2 access) + 0x0004 (Write only)
Dual-Port RAM = Slot base (Type 2 access) + 0x2000 (Read/write)
Part 2 - Interface cards Issue 2, June 1991 2-3