Service manual

Service Manual
The Intel chip set
As the Xerox and IEEE standards have become widely
accepted, a number of systems companies have produced
VLSI devices that considerably reduce the design effort
required to implement a connection. The most notable of
these are by Advanced Micro Devices (AMD) and Intel.
The Intel chip set comprising the 82586 local area network
coprocessor, the 82501 Ethernet serial interface, and the
82502 Ethernet transceiver chip has been used in this
design.
The 82586 and other similar local area network controllers
are generally referred to by the acronym LANCE, even
though this is a trademark of AMD.
The 82586 LANCE performs media access control,
framing, pre/postamble generation and stripping, source
address generation, CRC checking, and short packet
detection. In addition diagnostic functions such as Time
Domain Reflectometry (TDR) can be performed.
The 82501 serial interface adapter (SIA) performs
Manchester encoding/decoding, receives clock recovery
and directly drives the attachment unit interface (AU I) to
the cable mounted Ethernet transceiver. In addition the
82501 operates a watchdog to prevent continuous
transmission (a fault condition), and provides a loop-back
test facility. A second source for this device is SEEQ who
manufacturer a similar part, the DQ8023A. This part
however is not identical and will not perform TDR
correctly.
The 82502 transceiver applies transmit data to, and
removes receive data from the Cheapernet cable
interface. This devices performs a similar function to the
cable mounted Ethernet transceiver.
The dual port memory
The LANCE is a true coprocessor and is designed to
perform scatter-gather DMA. In common with other
LANCE chips the 82586 will utilise a significant bus
bandwidth when operating on a net running at 10 Mbps (
note: this is not simply the serial data rate divided by the
parallel bus width). This bandwidth cannot be provided by
the ARM processor over the podule bus and so a dual-port
memory system has been implemented.
All communication between the ARM and the LANCE is
carried out through command blocks in the dual-port RAM
(there are no visible registers in the 82586 LANCE). These
command blocks and associated data structures are
defined and described in Intel's data sheet.
To issue a command to the LANCE the ARM appends the
command to the command block list (CBL) in the dual-port
RAM. It then raises the channel attention (CA) signal to
the LANCE signalling the presence of the new command.
The LANCE responds to CA by reading the command
from the CBL and executing as required.
The LAN Components User's Manual contains a
considerably more detailed and comprehensive
description of the operation of the LANCE.
The control register
The control register contains four bits:
Reset (RST) Bit 0.
This bit controls the RESET pin on the LANCE. This bit
is set (LANCE reset) on system power-up/hard reset or
writing to the control register with this bit logic 1. This bit
is cleared (and the LANCE released from the reset state)
by writing to the control register with this bit logic 0.
Loop-Back (LB) Bit 1
This bit selects the loop-back mode of 82501 SAI chip.
This bit is set and the SIA chip put into loop-back mode
by the ARM writing to the control register with this bit
logic 1. This bit is cleared (SIA taken out of loop-back
mode) on system power-up/hard reset or writing to the
control register with this bit logic 0.
Channel Attention (CA) Bit 2
This bit generates a correctly timed CA pulse when the
ARM writes to the control register with this bit logic 1. No
CA pulse is generated if the ARM writes to the control
register with this bit logic 0.
Clear Interrupt (CLI) Bit 3
This bit clears the podule interrupt flag and removes the
podule interrupt when the ARM writes to the control
register with this bit logic 1. The podule interrupt and flag
are unaffected if the ARM writes to the control register
with this bit logic 0.
Each bit in the control register is not independent and
when writing to a particular bit, the remaining three must
be valid. The remaining 12 bits are ignored by the
hardware (zero is recommended).
Podule identification PROM
The podule identification PROM contains the following
information:
the Acorn podule identity number (03)
the interrupt (IRQ) flag bit
the PCB revision number
the six byte IEEE globally assigned address block
a CRC to allow the PROM to be validated. The
contents and operation of the interrupt flag are
described in Interrupts in Detailed description below.
Detailed description
Address map
The Ethernet I expansion card address map (offset
relative to slot base) is shown in Table 2-1: Ethernet I
expansion card address map. The RAM buffer occupies
the upper half of the podule address space. The ID
PROM, page register and control register occupy the
lower half.
2-2 Issue 2, June 1991 Part 2 - Interface cards