Service manual

Service Manual
The sound system
The sound system is based on the VIDC stereo sound
hardware. External analogue anti-alias filters are used
which are optimised for a 20 kHz sample rate. The high
quality sound output is available from a 3.5mm stereo
jack socket at the rear of the machine which will directly
drive personal stereo headphones or alternatively an
amplifier and speakers. One internal speaker is fitted, to
provide mono audio.
VIDC sound system hardware
VIDC contains an independent sound channel consisting
of the following components: A four-word FIFO buffers 16
8-bit sound samples with a DMA request issued
whenever the last byte is consumed from the FIFO. The
sample bytes are read out at a constant sample rate
programmed into the 8-bit Audio Frequency Register.
This may be programmed to allow samples to be output
synchronously at any integer value between 3 and 255
microsecond intervals.
The sample data bytes are treated as sign plus 7-bit
logarithmic magnitude and, after exponential digital to
analogue conversion, de-glitching and sign-bit steering,
are output as a current at one of the audio output pins to
be integrated and filtered externally.
VIDC also contains a bank of eight stereo image position
registers each of three bits. These eight registers are
sequenced through at the sample rate with the first
register synchronised to the first byte clocked out of the
FIFO. Every sample time is divided into eight time slots
and the 3-bit image value programmed for each register
is used to pulse width modulate the output amplitude
between the LEFT and RIGHT audio current outputs in
multiples of time slot subdivisions. This allows the signal
to be spatially positioned in one of seven stereo image
positions.
MEMC sound system hardware
MEMC provides three internal DMA address registers to
support Sound buffer output; these control the DMA
operations performed following Sound DMA ,requests
from VIDC.
The registers allow the physical addresses for the
START, PNTR (incremental) and END buffer pointers to a
block of data in the lowest half Megabyte of physical RAM
to be accessed.
These operate as follows: programming a 19-bit address
into the PNTR register sets the physical address from
which sequential DMA reads will occur (in multiples of
four words), and programming the END pointer sets the
last physical address of the buffer. Whenever the PNTR
register increments up to this END value the address
programmed into the START register is automatically
written into the PNTR register for the DMA to continue
with a new sample buffer in memory.
A Sound Buffer Interrupt (SIRQ) signal is generated when
the reload operation occurs which is processed by IOC as a
maskable interrupt (IRQ) source.
MEMC also includes a sound channel enable/disable
signal. Because this enable/disable control signal is not
synchronised to the sound sampling, requests will
normally be disabled after the waveforms which are being
synthesised have been programmed to decay to zero
amplitude; the last value loaded into the Audio data latch
in the VIDC will be output to each of the Stereo image
positions at the current Audio Sample rate.
IOC sound system hardware
IOC provides a programmed output control signal which
is used to turn the internal speaker on or off, as well as an
interrupt enable/status/reset register interface for the
Sound Start Buffer reload signal generated by MEMC.
The internal speaker may be muted by the control line
SMUTE which is driven from the IOC output C5. On reset
this signal will be taken high and the internal speaker will
be muted.
The stereo output to the headphone socket is not muted
by SMUTE and will always reflect the current output of
the DAC channels.
Part 1 - System description Issue 2, June 1991 1-9