Service manual
Service Manual
Interrupts
The I/O system generates two independent interrupt
requests, IRO and FIQ. Interrupt requests can be caused
by events internal to IOC or by external events on the
interrupt or control port input pins.
The interrupts are controlled by four types of register:
• status
• mask
• request
• clear
The status registers reflect the current state of the various
interrupt sources. The mask registers determine which
sources may generate an interrupt. The request registers
are the logical AND of the status and mask registers and
indicate which sources are generating interrupt requests
to the processor. The clear register allows clearing of
interrupt requests where appropriate. The mask registers
are undefined after power up.
The IRQ events are split into two sets of registers, A and
B. There is no priority encoding of the sources.
Internal Interrupt Events
• Timer interrupts TM[0:1]
• Power-on reset POR
• Keyboard Rx data available SRx
• Keyboard Tx data register empty STx
• Force interrupts 1.
External Interrupt Events
• IRQ active low inputs IL[0:7] wired as (0-7
respectively) PFIQ, SIRQ, SLC1, not used, DCIRQ,
PIRQ, PBSY and RII.
• IRQ falling-edge input IF wired as PACK
• IRQ rising-edge input IR wired as VFLY
• FIQ active high inputs FII[0:1] wired as FFDQ and
FFIQ
• FIQ active low input FL wired as EFIQ
• Control port inputs C[3:5].
Podule interrupt mask
Podule IRQ can be masked by writing a 0 to the Podule
IRQ mask register at &3360004. This will disable the
interrupt.
The request register at &3360000 is a logical AND of
Podule IRO and the mask register, ie it is1 if Podule IRO
is not masked.
IRQ status
A
Bit
Name
Function
0
PBSY
This bit indicates that the printer is
busy.
1
RI
This bit indicates that a Ringing
Indication has been detected by the
serial line interface.
2
Printer Ack
This bit indicates that a printer
acknowledgement bit has been
received.
3
Vert Flyback
This bit indicates that a vertical flyback
has commenced.
4
Power-on reset
This bit indicates that a power-on reset
has occurred.
[5:6]
Timer 0 and
These bits indicate that events have
Timer 1 events
occurred. Note: latched interrupt.
7
Force
This bit is used to force an IRQ request.
It is usually owned by the FIQ owner
Part 1 - System description Issue 2, June 1991 1-7