Specifications

4 Issue 5, August 1994 Acorn Enhanced Expansion Card
Acorn Enhanced Expansion Card
and D. The slowest cycle type is A and the quickest is D
– cycle types B and C fall in-between. Data can be
transferred to and from the expansion bus in chunks of
between 1 byte and a maximum of 4KB. Each DMA
channel has the capability of supporting two data
buffers, each of which can be up to 4KB in size, so that
data transfer speeds can be optimised by performing
DMA transfers from one buffer whilst the programming
of the other buffer takes place ready for the next block
transfer. The use of two large buffers (4KB) for DMA
transfers will achieve a close to continuous flow of data.
A full description of how a DMA channel is programmed
is beyond the scope of this document and can be found
in the RISC OS 3 Programmer’s Reference Manual,
Vol5 (version 3.5 supplement) part number 0497,551.
Data bus mapping
MEMC and IOC expansion cards
The I/O data bus (BD[0:15]) connects to the main system
data bus (D[0:31]) via a set of bidirectional data latches.
The mapping of the BD[0:15] bus onto the D[0:31] bus is
as follows:
• During a WRITE (i.e. MPU to peripheral), BD[0:15] is
mapped to D[16:31]
• During a READ (i.e. peripheral to MPU), BD[0:15] is
mapped to D[0:15].
DEBI and EASI expansion cards
During an EASI type access the I/O data bus (BD[0:31])
connects to the main system data bus (D[0:31]). The
lower 16 bits D[0:15] of the bus are latched through
IOMD, and the upper 16 bits D[16:31] are latched
externally through a set of data latches. The mapping of
the BD[0:31] bus onto the D[0:31] bus is as follows:
• During a WRITE (i.e. MPU to peripheral), BD[0:31] is
mapped to D[0:31]
• During a READ (i.e. peripheral to MPU), BD[0:31] is
mapped to D[0:31].
The data path for 32 bit DMA transfers is identical to the
above except transfers are between main memory and
the peripheral.
Byte accesses
To access bytewide expansion cards, byte instructions
should be used. When a StoreByte instruction is
executed, the ARM MPU will place the written byte on all
four bytes of the word, and will therefore correctly place
the desired value on the lowest byte of the I/O bus. A
byte or word load may be used to read a bytewide
expansion card into the lowest byte of an ARM register.
For example:
...
...
LoadByte
LDRB Rdata, [Raddress]
...
StoreByte
STRB Rdata, [Raddress]
...
...
Half-word accesses
To access a 16-bit wide expansion card, word
instructions should be used. When storing, the half-word
must be placed on the upper 16 bits, D[16:31] for MEMC
and IOC expansion cards. To maintain upwards
compatibility with future machines, half-word stores
should replicate the written data on the lower half-word,
D[0:15]. When reading, the upper 16 bits are undefined.
For example:
...
...
LoadHalfWord
LDR Rdata, [Raddress]
MOV Rdata, Rdata, ASL#16
MOV Rdata, Rdata, ASR#16
...
StoreHalfWord
MOV Rdata, Rdata, ASL#16
ORR Rdata, Rdata, Rdata, LSR#16
STR Rdata, [Raddress]
...
...
Word accesses
To access a 32-bit (word-wide) expansion card, a word
instruction should be used for both reads and writes to
expansion cards.
For example:
...
...
LoadWord
LDR Rdata, [Raddress]
...
...
StoreWord
STR Rdata, [Raddress]
...
...
Expansion card interrupt handling
There are two interrupt lines on the expansion card bus,
PIRQ and PFIQ. Both lines are vectored through the IOC
or IOMD and generate the ARM IRQ and FIQ signals
respectively. PIRQ is the normal interrupt request line,
and appears as bit 5 in the IOC or IOMD IRQ status B
register (hex address 03200020). PFIQ is the fast
interrupt request line, and appears as bit 6 in the IOC or
IOMD FIQ status register (hex address 03200030). For
further details on interrupt handling, refer to the IOC
and/or the IOMD data sheets.
An expansion card generating an IRQ interrupt must