Specifications

Appendix B Issue 5, August 1994 B-7
DMA Extended Bus Interface
Design considerations
It is recommended that all bus signals on an expansion
card that are to be used on multiple inputs or devices far
from the connector are buffered, with the buffer devices
being physically close to the signal connector.
Signals should not be presented with a capacitive load
greater than 20pF; this is equivalent to the connector
(5pF), 6cm of 0.2mm copper track (5pF), and 10pF input
capacitance of the buffer device (e.g. 74HC245 for data
lines). Unidirectional buffers will have lower input
capacitance (typically 3.5pF). Tracks should always be
kept as short as possible.
This gives worst case rise and fall times for all data bus
signals of 12nS. Other signals will be equal or better.
Figure 4 shows a recommended layout for buffer devices
on an expansion card. In practice it is unlikely that all 32
data bits and all 24 address lines would be used.
Additional space savings can be achieved by using
surface mount devices.
The direction of data bus buffers should be controlled by
LRNW and enabled by the combination of the required
select strobes and the nBW signal.
Clock signals may be buffered with AC logic where their
timing in relation to other bus signals is critical to the
proper operation of the design.
Power consumption limitations must be adhered to and
consideration must be given to potential noise generated
by many outputs switching simultaneously. If all 32 data
lines are to be driven, extra smoothing of the +5v rail may
be required, or a system of staggered buffer enabling
added. As a matter of course all power rails in use should
be smoothed with 47uF electrolytic capacitors, in addition
to the 100nF decoupling provided close to each digital
integrated circuit device.
Four-layer PCBs will provide cleaner power supply rails
and make the task of keeping track lengths within
recommended limits easier. However, it is permissible to
use two-layer PCBs, provided that power tracks are the
optimum thickness to keep impedance to a minimum,
and component density is low.
Risc PC expansion bus backplane
The motherboard of the Risc PC provides a 132-way
edge connector for use with plug-in backplane add-ons.
Electrically, the Risc PC I/O interface supports
backplanes with up to 8 slots. All decoding needed to
interface the relevant select signals per slot is provided
on the plug-in backplane.
Firmware support
Full support is provided for expansion card driver
software located in the extended address area. This
means that an expansion card utilising the extended
address space need not have ROM located in IOC space
and as a consequence no page latch is required.
A ROM located in the extended address space may be
byte, half-word or word wide. Driver firmware must be
transferred to DRAM before being executed; it cannot be
executed in place.