Specifications

Appendix B Issue 5, August 1994 B-5
DMA Extended Bus Interface
DRQ timings
Design notes
It is allowable to keep DRQ asserted if a peripheral wants
to perform multiple DMA cycles. The removal of DRQ at
the end of a multiple transfer must still adhere to t2 and
t3.
Once asserted DRQ should never be de-asserted before
a responding DACK low as occurred (see t3).
1. The maximum figure will vary depending on cycle
type, i.e. width of DACK. The only requirement for a
maximum figure is that DRQ is de-asserted a mini-
mum of 15nS before DACK rises (see t2).
Table 5: DRQ timings
Sym. Description Min Typ Max Units
t1
DACK low from CLK16
low
0 20 ns
t2 DRQ low to DACK high 30 ns
t3 DACK low to DRQ de-
assert
5 See
below
1
ns
If DRQ is de-asserted during DACK low, it should only be
re-asserted a minimum of 40ns after DACK goes high.
Figure 3: DRQ timings
CLK16
t1
t2
t3
DRQ
DACK