Specifications

B-4 Issue 5, August 1994 Appendix B
DMA Extended Bus Interface
DMA access timings
The DMA access timings for Cycle types A, B, C, and D
are as follows:
Table 4: DMA access timings
Sym. Description Cycles Min Typ Max Units
t0 CLK16 clock cycle all 62.5 ns
t1 Clock low to
DACK
low
all 0 20 ns
t2 Clock low to TC high all 0 20 ns
t3 DACK strobe width A 427 ns
B 302 ns
C 175 ns
D 115 ns
t4 DACK low to IORD
or IOWR low
A, B 80 ns
C, D 15 ns
t5 IORD or IOWR high
to DACK high
A 80 ns
B, C, D 15 ns
t6 IORD or IOWR
strobe width
A 240 ns
B 175 ns
C 115 ns
D 52 ns
t7 TC strobe width A 427 ns
B 302 ns
C 175 ns
D 115 ns
On future machines the DEBI may not use CLK16 as the
master clock. It is not therefore recommended that
CLK16 is used. The edge relationship of CLK16 to the
other interface signals cannot be relied upon for simple
state machine design. It is recommended that expansion
cards contain their own ‘on-board’ clock to synchronise
the interface signals.
Note: The LRNW timings of t12 and t13 may not be
supported on future platforms.
t8 Read data setup to
IORD high
all 35 ns
t9 Read data hold from
IORD high
all 10 ns
t10 Write data setup to
IOWR low
all 10 ns
t11 Write data hold
from IOWR high
all 25 ns
t12 LRNW active to
DACK low
all 10 ns
t13 LRNW in-active
from DACK high
all 10 ns
Table 4: DMA access timings (Continued)
Sym. Description Cycles Min Typ Max Units
Figure 2: DMA access timings
CLK16
Read data
Write data
t1
t2
t3
t4
t5
t6
t7
t8 t9
TC
t0
t12
t13
t10
t11
DACK
LRNW
IORD
IOWR