Specifications

Appendix B Issue 5, August 1994 B-3
DMA Extended Bus Interface
Signal timings
Extended address space (EASI) timings
The Extended Address Space Interface (EASI) access
timings for cycle types A and C are as follows:
Table 3: EASI access timings
Sym. Description Cycles Min Typ Max Units
t0 CLK16 cycle time all 62.5 ns
t1 Clock falling edge
to
EAS low
all 0 20 ns
t2 Address and nBW
setup to EAS low
all 10 ns
t3 Address and nBW
hold from EAS high
all 10 ns
t4 EAS low to IORD
or IOWR
A 80 ns
C 15 ns
t5 IORD or IOWR
high to EAS high
A 80 ns
C 15 ns
t6 IORD or IOWR
low to Ready low
A 50 ns
C 50 ns
t7 Ready high to
IORD or IOWR
high
A 0 265 ns
C 0 140 ns
t8 Read data setup
to IORD high
all 20 ns
On future machines the DEBI may not use CLK16 as the
master clock. It is not therefore recommended that
CLK16 is used. The edge relationship of CLK16 to the
other interface signals cannot be relied upon for simple
state machine design. It is recommended that expansion
cards contain their own ‘on-board’ clock to synchronise
the interface signals.
t9 Read data hold
from IORD high
A 10 90 ns
C 10 90 ns
t10 Write data setup to
IOWR low
all 10 ns
t11 Write data hold
from IOWR high
all 25 ns
t12 EAS select width A 427 ns
C 175 ns
t13 IORD and IOWR
strobe width
A 240 ns
C 115 ns
t14 LRNW active to
EASI low
all 10 ns
t15 EASI high to
LRNW in-active
all 10 ns
t16 Ready Strobe
width
all 0ns 2µS
Table 3: EASI access timings (Continued)
Sym. Description Cycles Min Typ Max Units
Figure 1: Extended address space (EASI) timings
CLK16
LA[0..23]
Ready
Read data
Write data
t1
t2 t3
t4
t5
t6
t7
t8 t9
t11
t12
t13
t0
nBW
t14
t15
t16
t10
IOWR
LRNW
EAS
IORD