Specifications

B-2 Issue 5, August 1994 Appendix B
DMA Extended Bus Interface
Description of signals
The following table shows the complete pin-out of the
Acorn enhanced expansion bus. The DEBI specific
signals are shown in bold and described in this section.
1. The Risc PC only supports DMA on slots 0 and
1 of the backplane
Table 1: Acorn enhanced expansion bus pin-out
Pin A B C
1 0v 0v 0v
2 LA[15] nBW -5v
3 LA[14] LA[23] 0v
4 LA[13] LA[22] 0v
5 LA[12] LA[21] Ready
6 LA[11] LA[20]
MS
7 LA[10] LA[19] DRQ
1
8 LA[9] LA[18] DACK
1
9 LA[8] LA[17] Reserved
10 LA[7] LA[16] Reserved
11 LA[6] LA[1] TC
1
12 LA[5] LA[0]
RST
13 LA[4] 0v PR/W
14 LA[3] BD[31] IOWR
15 LA[2] BD[30] IORD
16 BD[15] BD[29] PIRQ
17 BD[14] BD[28] PFIQ
18 BD[13] BD[27] EAS
19 BD[12] BD[26] I2Cclk
20 BD[11] BD[25] I2Cdat
21 BD[10] BD[24] Reserved
22 BD[9] 0v PS
23 BD[8] BD[23] IOGT
24 BD[7] BD[22] IORQ
25 BD[6] BD[21] BL
26 BD[5] BD[20] 0v
27 BD[4] BD[19] CLK2
28 BD[3] BD[18] CLK8
29 BD[2] BD[17] REF8M
30 BD[1] BD[16] +5v
31 BD[0] 0v CLK16
32 +5v +5v +12v
The functional descriptions of the signals are as follows:
Note: On the Risc PC, the upper sixteen data lines
BD[31:16] are driving at all times except:
• During DMA reads
• During reads from EASI space
Consequently, any expansion card with data bus buffers
connected to the upper sixteen data bits should not
enable them for output except during extended address
space and DMA reads.
DMA control
A full explanation of the use of the DMA control registers
is beyond the scope of this document. Please refer to the
RISC OS 3 Programmer’s Reference Manual for further
details of the DMA channel control registers and DMA
data transfers.
Table 2: Functional description of signals
Signal Type Description
LA [0..23] type O Latched version of the main system address
bus.
BD[0..31] type I/O Buffered version of the main system data bus,
see note.
nBW type O When low indicates byte wide access; when
high indicates word or half word access. Not
used during DMA transfers.
Ready type I Used to stretch EASI access cycles. Active low.
DRQ type I DMA request. Active high.
DACK type O DMA acknowledge. Active low.
TC type O Terminal count. Indicates last cycle of DMA
transfer is taking place. Active high.
PR/W type O When high, this signal indicates that the cycle
taking place is a read cycle, when low it
indicates that a write cycle is taking place.
IOWR type O Write strobe for I/O space access cycles.
Active low.
IORD type O Read strobe for I/O space access cycles.
Active low.
EASI type O EASI address space select signal. Active low.
CLK16 type O 16MHz system clock.