Specifications

20 Issue 5, August 1994 Acorn Enhanced Expansion Card
Acorn Enhanced Expansion Card
Figure 21: MEMC expansion card timing
PH2
REF8M
IORQ
IOGT
MS
BL
write
BL
read
BD[0:15]
write
BD[0:15]
read
LA[2:15]
t37
t33
t38
t29
t31
t26
t27
t30
t25
t32
end of cycle (retry)
end of cycle (first try)
t36
t39
t24
t28
t34
t35
t26
Sym Parameter Min Max
t24 IORQ setup (first attempt) 70 115
t25 IORQ setup (retries) 50 75
t26 IORQ hold 50
t27
IOGT setup 25 120
t28 IOGT hold 20 100
t29
MS setup to REF8M
3
110
t30 MS hold 5
t31 BL delay write 0 65
t32 BL hold read 10 100
t33 BD[0:15] setup write 85
1
t34 BD[0:15] hold from BL write 5
t35 BD[0:15] setup to REF8M read 50
2
t36 BD[0:15] setup to
BL read 20
t37 BD[0:15] hold from BL read 15
t38 LA[2:15], PR/W setup to REF8M 140
t39 BL Read delay 60
1
with BL high i.e. buffers transparent.
2
setup to the earliest possible end of cycle.
3
the first rising edge of REF8M after IORQ goes low.