Specifications

Acorn Enhanced Expansion Card Issue 5, August 1994 19
Acorn Enhanced Expansion Card
A MEMC I/O cycle is shown in Figure 18 below. The
cycle starts with IORQ being taken low. There follows a
number of 8 MHz clock ticks until the I/O controller is in
a position to complete the cycle. The IOGT line is taken
low, and both MEMC and the I/O controller see IORQ
and IOGT low on the rising edge of REF8M, so the I/O
cycle terminates on the next falling edge of REF8M.
Figure 18: I/O cycle
Some I/O cycles may only take 250ns as shown in
Figure 19 below. To give the I/O controller adequate
time to recognise such operations, MEMC produces the
first IORQ early in the I/O cycle.
The extension of IORQ only happens at the start of an
I/O cycle; if the IORQ signal is removed during a DMA or
refresh operation, it will be reasserted when REF8M
goes low.
Figure 19: Fast I/O cycle
I/O cycles may be interrupted by DMA and refresh
operations, as shown in Figure 20 below. If a DMA or
refresh operation is pending, the IORQ signal is driven
high when REF8M next goes low. The DMA/refresh
operation may then begin. When the operation
completes, the I/O cycle is resumed by setting IORQ low
(provided no more DMA or refresh operations are
pending). The DBE line is always driven low by MEMC
during DMA/refresh operations to disable the processor
data bus drivers. Hence the I/O cycle is stretched, and
the write data would become invalid during the cycle.
The data must therefore be latched into the data bus
buffers by the I/O controller during the first IORQ low
period, and be held until the I/O cycle has completed.
This is done by the I/O controller driving BL low for this
period. The maximum time for which an I/O cycle may be
interrupted in this way is 1875ns (i.e. 15 REF8M cycles).
PH2
REF8M
IORQ
IOGT
PH2
REF8M
IORQ
IOGT
Figure 20: I/O cycle interrupted by a DMA or refresh
operation
Note: Care must be taken not to address a non-existent
I/O controller, as MEMC will hold the processor clocks
indefinitely until a low is seen on the IOGT line, or
RESET is set high.
PH2
REF8M
IORQ
IOGT
Operation
DMA or Refresh End of
I/O Cycle
Start of I/O cycle