User's Manual

If WAIT is permanently low, or high, check TP7 after pressing BREAK;
the WAIT signal should go low and then high. If not, check that (0) is
clocking IC16A and B and IC30A and B (for HCS/PCS WAIT) and that the
desync. circuits are producing the correct WAIT outputs. See section
5.9.
6.3.4 ROM Signal/Break
On power-up, the RC network R1, C2, D1 provides a low to high
transition of approximately 0.1 second duration to pin 9 of IC19C. If
power-up reset fails and the low to high transition time is found to
be incorrect, check these component values and replace as necessary.
After power-up, pressing and releasing the BREAK key on the host
keyboard causes PRST to appear on pin 37 of Tube IC1. This is clocked
through IC15B by Ml. Thus, if the CPU is halted for any reason, M1
will not be present and a BREAK reset will not be possible, i.e. a
successful power-up reset is necessary to a11ow any further resets to
work.
The low signal should clock to monostable IC14 which should produce a
signal of approximately 10µs duration. If not, check the values of RC
network R7/C8 and replace if necessary.
The output of IC14 appears at pin 10 of IC19C; from here on the reset
function is common to both power-up and BREAK, as follows:
The reset signal from IC19C is inverted by IC24F and appears at pin
26 of IC2 (CPU reset) and also at pin 3 of IC 15A (ROM latch) so
that, if 1C15A is functioning correctly, a reset should cause a low-
going pulse to appear at IC2 pin 26 (reset active low), followed by a
low on TP2 (ROM). This signal must appear at pin 18 of IC3 and
requires both MREQ and RD to be both active low to pass IC22C and
output enable IC3 on pin 20 (and disable CAS at IC21D, pin 13).
The active-low ROM signal at IC22C also appears at pin 2 of IC16A
which enables WAIT states at pin 24 of IC2 (see Wait State Generator,
above). Using an oscilloscope, check that all these events occur,
replacing any failed components.
After ROM on TP2 has remained low for approximately 0.25s, the CPU
executes an instruction fetch from high memory, M1 and MREQ both go
to active low and their inverted signals appear at pins 3 and 5
respectively of IC20B. This, combined with A15 high should produce a l
ow at pin 6 which, via IC24C will clear IC15A at pin 1 and remove the
ROM signal. Again, check all conditions with an
oscilloscope and correct any failed logic.