User's Manual

6. Fault Finding on the Z80 Second Processor
6.1 General
a) The Z80 second processor has three socketed IC's (IC 1 - 3) -
these may easily be replaced if necessary.
b) Test points are provided on the Z80 PCB, as fo11ows:
TP1 CLOCK 6MHz clock signal 0 to pin 6 of Z80
processor
TP2 ROM disable/activate signal to ROM, pins 18 &
20
TP3 M1 Z80 generated clock signal indicating an
instruction-fetch cycle. Also used in
interrupt handling.
TP4 MREQ goes low to indicate memory addressing
TP5 PCS indicates successful parasite chip select
to Tube, via de-sync logic circuit
TP6 HCS indicates Post chip select to tube
TP7 WAIT Occurs during reads from the ROM and as
result of simultaneous HCS/PCS event.
Enables refresh cycles
TP8 RAS Row Address Signal, used in ALL memory
addressing, both for accessing and
refreshing
TP9 CAS Column Address Signal, used only for
memory accessing, disabled during
refresh
6.2 Fault Conditions
A Z80 Second Processor failure can usually be related to one of
five fault conditions: