User's Manual

DESCRIPT1ON OF PINS (ref. Fig.7):
Power Supply GND 0V supply rail
VCC1 Parasite main +5V supply
VCC2 Parasite secondary supply (+2-3v)
VCC3 Host +5V supply
Data buses HD0-7 8-bit data bus to Host processor
PD0-7 8-bit data bus to Parasite
processor
Address signals HA0-2 3 register select lines from Post
PAO-2 3 register select lines from
Parasite
PCS Post chip select
PCS Parasite chip select
Timing signals P42 Host $2 - high level signifies
valid address bus
PR/W Post read/write line - determines
whether read or write register is
selected on address specified by
PAO-2, and direction of data flow
on PD0-7
PNRDS Parasite read strobe (active-low)
PNWDS Parasite write strobe (active-low)
Interrupt lines PRST Host reset (RST) -initialises Tube
to known state and generates PRST
PRST Reset (RST) line to parasite
processor
PNM1 Non-maskable interrupt to parasite
PIRQ Interrupt to Host (not used by Z80
second processor)
DMA lines DRQ Request for DMA transfer
DACK DMA acknowledge from DMA controller
DMA facility is not used by the Z80 second processor