User's Manual

Fig. 3 Instruction-Fetch cycles
5.8 DRAM Refresh
After each instruction-fetch, the Z80 CPU performs a Refresh cycle for
the DRAMS in the period while the instruction is being decoded. A
seven-bit refresh address is output onto the address-bus (A0 to A6, A7
=0) for approx. 2 clock cycles, and the MREQ signal goes low. The "
RFSH" signal from the Z80 is not used, and no other