User's Manual

Fig. 2 RAM read or write cycles
CAS is enabled if:
i. the memory cycle is a
write cycle (WR
low, to IC20C pin
11).
or ii. the memory cycle is
a read cycle and
not an
instruction-fetch
cycle (IC18B not
preset by Ml, RED
signal to IC20
pin 9).
or iii. the cycle is an
instruction-fetch
this signal being
synchronised to
the CPOP signal by
OR gate 1C23B (to
IC20 pin 10)
Note: In this case, the
CAS signal will
not be generated
if the ROM is
selected.
5.7.2 Instruction-Fetch Cycles
The Z80 CPU handles an Instruction Fetch differently to other memory
read cycles, in that the MREQ signal is active for only 1.5 clock
cycles instead of 2. In order to allow sufficient access time for the
DRAMS in this abbreviated cycle, the Instruction-Fetch signal, Ml, is
used to generate the RAS and CAS signals a half-cycle earlier. The OR
gate IC23A allows the clock signal through to the "D" latch IC18A,
only when M1 is active. The output of the "D" latch, SUE is clocked
low, and generates the row-address latch signal RAS, a half clock
cycle before the CPOP signal would have done. When the CPOP signal
arrives after being generated by the MREQ (see section 5.7.1a), it
clears the SUE latch and holds RAS low itself until MREQ becomes
inactive.