User's Manual

is detected. IC26 and IC27 provide a clock signal, NMISERV during such
a cycle, which presets the ROM latch IC15A, latching the ROM in until
an instruction-fetch from high RAM. In the ROM, 66H contains a jump to
the destination expected by standard CPM.
Because of the slow access time of the "boot" ROM, all memory cycles
to the ROM must be lengthened by the insertion of a "Wait-State" of
one clock cycle. When the ROM is selected, the OR gate IC22C provides
the OE signal to the ROM and this is used to enable the Wait-State
generator IC16A&B. Via the NAND gate IC21C, a low-going pulse of 1
clock cycle is fed to the WAIT input of the Z80 (see timing diagram
above). The Wait generator requires a further two clock cycles after
the end of the lengthened memory
cycle to clear itself. The Z80 samples the WAIT input on the
falling edge of 0 (t
1
). TP7 a11ows observation of the WAIT signal.
5.5. Reset
The Z80 second processor may be reset at any time, by the host
processor via the Tube.
The Z80 requires that a reset signal should not occur immediately
after an instruction fetch cycle, otherwise corruption of DRAM data
might result. To avoid this, the "D" latch IC15B synchronises the
reset signal from the Tube to the beginning of an instruction-fetch
cycle (M1). A monostable IC14 ensures the reset