Z80 SECOND PROCESSSOR SERVICE MANUAL Part No.
Within this publication the term 'BBC' is used as an abbreviation for 'British Broadcasting Corporation'. °Copyright Acorn Computers Limited 1984 Neither the whole or any part of the information contained in, or the product described in, this manual may be adapted or reproduced in any material form except with the prior written approval of Acorn Computers Limited (Acorn Computers). The product described in this manual and products for use with it, are subject to continuous development and improvement.
CONTENTS Page 1 Introduction 1 2 Packaging and Installation 2 3 Specification 3 4 Disassembly and Assembly 4 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 Circuit Description CPU Clock ROM Latch Wait-States Reset Interrupt Handling DRAM Control DRAM R e f r e s h Desynchronising Logic The Tube 5 5 5 5 6 6 7 7 9 10 11 6 6.1 6.2 6.
WARNING: THE Z80 SECOND PROCESSOR MUST BE EARTHED Important: The wires in the mains lead for the.
1. Introduction This manual is intended to provide the information required to diagnose and repair faults on the Z80 second processor (a part of the BBC Microcomputer system) which was designed by Acorn Computers Ltd. of Cambridge, England. The information contained in this manual is aimed at Acorn dealers and service engineers who will be servicing the Z80 second processor on behalf of Acorn Computers Ltd. Z80 is a trademark of Zilog Inc. CP/M® is a registered trademark of Digital Research Inc.
2. Packaging and Installation. The Z80 second processor is supplied in a two-part moulded polystyrene packing which is further packaged within a cardboard sleeve. Supplied with the second processor is a DNFS ROM with fitting instruction sheet, a set of reminder cards for the red function keys, 7 floppy disks, an end-user licence and a guarantee card. For BBC Microcomputers fitted with MOS ROMs below version 1.2, a voucher redeemable against replacement of lower version ROMs, is also supplied.
3. Specification 3.1 The Z80 second processor A second processor for the BBC Microcomputer model B, operating through the Tube, providing the ability to run sophisticated software under the CP/M 2.2 operating system.
4. Disassembly and assembly To service the Z80 second processor, disconnect it from the BBC Microcomputer and the mains supply and undo the three fixing screws; two at the top of the back panel and one underneath the unit, nearest the front and equidistant between the two rubber feet. (The assembly diagram is given in the Appendix). The lid can now be removed revealing the transformer and power supply board, held in place by six screws, and the Z80 PCB.
5. Circuit Description The circuit may be split into a number of sections by their specific function. These are dealt with under separate headings. Reference should be made, where necessary, to the block diagram and circuit diagram in the appendix. 5.1 CPU The microprocessor used in this unit is a Z80B, running at a clock frequency of 6MHz from a crystal oscillator.
is detected. IC26 and IC27 provide a clock signal, NMISERV during such a cycle, which presets the ROM latch IC15A, latching the ROM in until an instruction-fetch from high RAM. In the ROM, 66H contains a jump to the destination expected by standard CPM. Because of the slow access time of the "boot" ROM, all memory cycles to the ROM must be lengthened by the insertion of a "Wait-State" of one clock cycle.
signal to the CPU is a pulse of approx. 4µs duration, sufficient to produce a reset without delaying the refresh to the DRAMS and so losing data. The reset to the CPU also clears the ROM latch IC15A, bringing the shadow ROM into the memory-map. The Schmitt NAND gate IC19C provides a Power-Up reset to' the Z80 from the delay network R1, C2 (time-constant 100ms). Diode D1 ensures that the capacitor does not apply a reverse voltage to the NAND gate input on Power-Down. 5.
CAS is enabled if: i. the memory cycle is a write cycle (WR low, to IC20C pin 11). or ii. the memory cycle is a read cycle and not an instruction-fetch cycle (IC18B not preset by Ml, RED signal to IC20 pin 9). or iii. the cycle is an instruction-fetch this signal being synchronised to the CPOP signal by OR gate 1C23B (to IC20 pin 10) Note: In this case, the CAS signal will not be generated if the ROM is selected. Fig. 2 RAM read or write cycles 5.7.
Fig. 3 Instruction-Fetch cycles 5.8 DRAM Refresh After each instruction-fetch, the Z80 CPU performs a Refresh cycle for the DRAMS in the period while the instruction is being decoded. A seven-bit refresh address is output onto the address-bus (A0 to A6, A7 =0) for approx. 2 clock cycles, and the MREQ signal goes low.
memory control signals go active. The Refresh address is incremented by the CPU after each time. Once the MREQ signal goes active, the "D" latch 1C18B produces CPOP and hence RAS as normal. The CAS is not required for a Refresh cycle, and is not enabled since none of the conditions listed in section 5.7. 1b are true (AND gate IC20C). When the shadow ROM is being read, the CAS signal to the DRAMS is disabled, but the row-address latch signal, RAS, sti11 occurs.
5.10 The Tube The Tube (IC1) is an Acorn custom IC which provides parallel asynchronous communication between two processor systems, the BBC Microcomputer (Host) and the Z80 second processor (Parasite). To each processor system, it resembles a conventional peripheral device comprising 4 read-only and 4 write-only, 8-bit registers. The Z80 accesses these registers via its I/O structure. Fig. 5 Tube concept 5.10.
Fig.
The fo11owing tables show the relative address and type of each register in the Tube, firstly for the Host system, and secondly for the parasite system (second processor).
As can be seen from Fig. 6 and Tables 1 and 2, each numbered register (e.g. register 1) is actually two registers, one for reading and one for writing. The register selected is determined by R/W on the Post system and by NRDS/NWDS on the Parasite system (see Tube Pinout Diagram). Only registers 2 and 4 are simple latches; register 3 is a 2-byte FIFO in each direction and register 1 is a 24-byte FIFO from the Parasite (Z80) to the Post, but a simple latch from Post to the ' Parasite.
DESCRIPT1ON OF PINS (ref. Fig.
5.10.3 Tube Timing Diagram Fig. 8 Tube Timing Diagram N.B.The timing reference for the Post is 0 and R/W gives the direction of transfer. For the parasite, the PCS direction is given by PNRDS or PNWDS, and timing by PCS.
6. Fault Finding on the Z80 Second Processor 6.1 General a) The Z80 second processor has three socketed IC's (IC 1 - 3) these may easily be replaced if necessary. b) Test points are provided on the Z80 PCB, as fo11ows: TP1 CLOCK 6MHz clock signal 0 to pin 6 of Z80 processor TP2 ROM disable/activate signal to ROM, pins 18 & 20 TP3 M1 Z80 generated clock signal indicating an instruction-fetch cycle. Also used in interrupt handling.
"BBC Microcomputer 32k..." message displayed. Predominantly caused by either power failure, misconnected or damaged plugs and/or interconnecting cable. "Acorn TUBE Z80 64k ..." message displayed; no response to Keyboard. If this message is displayed, the ROM has been copied completely to RAM , the ROM disabled and the Boot procedure begun. Failure to respond to the keyboard means that the system has crashed due to either hardware or software failure.
6.3 Circuit Checks 6.3.1 Clock Using an oscilloscope, check that a 12MHz signal is being generated at pin 13 of IC22D. If not, check the crystal X1, resistor values and operation of inverters IC24D/E. Trace the signal to pin 9 of IC17A where it should appear as a clearly defined 6MHz square wave (0). 4) should appear from the driver Q1 to supply IC2 pin 6. Check that the clock signals, 4) and appear at all the expected points shown on the circuit diagram.
If WAIT is permanently low, or high, check TP7 after pressing BREAK; the WAIT signal should go low and then high. If not, check that (0) is clocking IC16A and B and IC30A and B (for HCS/PCS WAIT) and that the desync. circuits are producing the correct WAIT outputs. See section 5.9. 6.3.4 ROM Signal/Break On power-up, the RC network R1, C2, D1 provides a low to high transition of approximately 0.1 second duration to pin 9 of IC19C.
6.3.5 Desynchronising Logic and PCS Disable HCS After power-up, check that PCS is active at pin 18 of IC1. If not, then either the Tube 1C1 or IC29 has failed on the second processor side, there is a ribbon cable/connector fault, or the Host is faulty. PCS After pressing BREAK, check that a low signal appears simultaneously at pins 1 and 2 of IC22A and that this appears at pin 3. Check that a low then appears at pin 21 of IC1; if not, the Desync. logic circuit is faulty.
address lines are shorted together and that all data lines are operating and not tied together. 6.3.9 Power Supply Check the 250 mA. type T mains fuse, accessible at the rear of the unit (see section 2). Check for any loose, disconnected or broken leads. After making sure that the second processor is disconnected from the mains supply, check the mains switch at the rear of the unit. Overload protection of the second processor is provided on the second processor Z80 board itself.
Fig. 9 Position of +5V Trimmer on Power Supply PCB. If the current is zero, the second processor PCB has gone open circuit. Check fuse FS1 and connectors and tracks. If the fuse is blown, the fault is a short circuit on the PCB. If the current is higher than it should be, measure the voltage. If the voltage is greater than 5.25V, adjust it to 5V using the trimmersee fig. 9. If the voltage is in spec., then one or more of the components on the second processor PCB is faulty.
Diagnostic Flowcharts Note: The letters in circles refer to the relevant flowcharts which follow.
27
Power Supply 3 5
Z80 Second Processor Functional Block Diagram
Z80 second Processor PCB Circuit Diag
Z80 PCB Silk Screen 43
Power Supply Circuit Diagram
Z80 Second Processor General Assembly 47
Z80 Second Processor Parts Lists NOTE: Items indentified by * are norma11y available as spare parts - please availability. ITEM PART No.
Z80 PCB Assembly (SEE 31 32 33 34 35 36 37 38 39 40 41 42 43 45 46 47 48 50 51 53 54 55 56 50 704,164 * 742,123 * 741,074/ 748,074 * 742,074 * 742,132 * 742,011 * 742,000 * 742,032 * 741,004 * 742,004 * 742,260 * 742,133 * 800,037 * 791,000 783,906 * 880,049 820,120 * 815,007 * 860,002 * 815,910 800,200 795,006 794,148 PAGE 41) - cont'd INTEGRATED CIRCUIT 8264 INTEGRATED C1RCUIT 74LS123 1NTEGRATED CIRCUIT 74S74/74F74 8 1 2 IC6-13 IC14 IC15 INTEGRATED CIRCUIT 74LS74 INTEGRATED CIRCUIT 74LS132 INTEGRAT
