Synthesis User Guide Using Synplify-Pro to target Speedster22i HD devices UG018 – April 15, 2013 UG018, April 15, 2013 1
Table of Contents Introduction ....................................................................................................... 3 Synplify Pro Introduction .................................................................................. 4 Resource Sharing .......................................................................................................................... 6 Verilog...................................................................................................................
Synthesis User Guide Introduction This User Guide describes how to use Synplify Pro from Synopsys to synthesize a design and generate a netlist for implementation on an Achronix Speedster22i HD device. Suggested Optimization Techniques are also included. Synplify-Pro reads in standard RTL and outputs a Mapped netlist which is used by the Achronix CAD Environment (ACE) tool. The netlist file uses a .vma extension. A high level overview of the Achronix design flow is shown in Figure 1 below.
Synplify Pro Introduction We assume you have Synplify-Pro installed and the ‘synplify_pro’ command added to your $PATH. This guide uses Unix for examples, the Windows version of Synplify Pro has the same options. In the Linux command shell type “synplify_pro” to invoke the Synplify-Pro Synthesis tool.
Select or click on the “New Project” button, then the following window will appear (shown in Figure 4): Figure 4 – Properly select the Project database for the synthesis. After selecting and saving the project file inside the desired directory path, you will have to add the source RTL files. There are two ways to add the source RTL files. One is using the “Add File” option from the Left menu bar and the other one is to ‘right click’ on the project file and select “Add Source File”.
After adding the RTL files, the next step is to set the Implementation Options. By selecting this option the following window will appear (Shown in Figure 6): Figure 6 – Implementation Options This dialog box shows the default options. For example the “Fanout Guide” defaults to 10,000, but you can modify this to any value. You can also check or uncheck the “Hard limit to Fanout” option as well as the “Disable I/O Insertion” option.
“Library Directories”. By default these two boxes are left empty. If user wants to add these paths, check the + switch and add the desired directory path. Place and Route This tab is not presently utilized by the Achronix back-end tool (ACE). Timing Report This tab will generate the timing report for the user after synthesis has completed.
Synthesis Optimization Recommendations There are several recommendations that can be implemented by the user during Synplify-Pro synthesis. This sections covers: Hanging Nets Clock Constraints Pipelining Retiming Memories o Block RAM (BRAM) o Local Ram (LRAM) Finite State Machines o Finite State Machine (FSM) Compiler o Replication of States that have high fan-ins Hanging Nets Synplify Pro always performs optimization on the redundant or feed-through nets.
Clock Constraints It is a requirement for the user to define all clocks with a specific duty cycle and frequency or clock period goal. The user can have multiple clocks with different clock frequencies. The default frequency can be set for all clocks with the set_option -frequency Tcl command in the Synplify project file. If the user does not specify a global frequency, the timing analyzer uses a default. Achronix does not recommend using the default.
-freq -period -clockgroup honored: Top-level output ports Input pins of instantiated gates Pins of inferred instances Defines the frequency of the clock in MHz. The user can specify either this or -period, but not both This parameter allows the user to specify the period of the clock in nanoseconds. The user can specify either this or -freq, but not both. This parameter allows the user to specify clock relationships.
During synthesis Synplify Pro will infer the BRAM80K block based on the above coding style.
Local Ram (LRAM) Distributed RAM or LRAM inferring or instantiation: Synplify-Pro is able to infer (or instantiate) LRAMs. With the current Synplify release, there must be a register at the output of the read port or the read address has to be registered to infer the LRAM. Inferred asynchronous reads from the LRAM are not yet supported. Also, with the current Synplify release, initializing the LRAM is not yet supported.
encoding. The FSM compiler can be disabled via the GUI or the from the Synplify project file with the following syntax: set_option –symbolic_fsm_compiler 0 The user may also direct the synthesis process to deploy a user-defined FSM encoding. An example: VHDL: attribute syn_enum_encoding of state_type: type is “001 010 101” ; There is a synthesis attribute to turn on/off FSM extraction. By using this attribute the user can see how state machines are extracted.
Figure 7- Replicated High Fan-in State Example Both state machines in the above Figure 7 are equivalent in function, but State A is duplicated in Version II so that A and A1 have two or less return inputs. As a result, if each state has to deal with two additional inputs, they can now be contained in one 4‐input LUT. Although this example is simplistic, the methodology can be applied to larger and more complex state machines. Fanout Limit: This fanout limit can also be controller through RTL design.
Example Synplify-Pro Project File #-- Synopsys, Inc. #-- Version F-2011.09X Beta #-- Project file /home/testing_HD.prj #project files add_file -verilog "//Achronixlinux/libraries/device_models/22i_synplify.v" add_file -vhdl -lib work " package1.vhd" add_file -vhdl -lib work "top_level.
# Compiler Options set_option -compiler_compatible 0 set_option -resource_sharing 0 # Compiler Options set_option -vhdl2008 1 #automatic place and route (vendor) options set_option -write_apr_constraint 1 #set result format/file last project -result_file "./rev_1_HD/.vma" impl -active "rev_1_HD" Note - if the user has a clock-constraint file for synthesis, in this case the user needs to add the following command inside the synthesis project file: #CONSTRAINTS add_file -constraint ".
Revision History The following table shows the revision history for this document. UG018, April 15, 2013 Date Version 2/6/2012 4/15/2013 1.0 1.1 Revisions Initial Achronix release. Corrected links.
