Speedster22i Pin Connections and Power Supply Sequencing User Guide UG042 – August 19, 2014 UG042, August 19, 2014 1
Copyright Info Copyright © 2014 Achronix Semiconductor Corporation. All rights reserved. Achronix is a trademark and Speedster is a registered trademark of Achronix Semiconductor Corporation. All other trademarks are the property of their prospective owners. All specifications subject to change without notice. NOTICE of DISCLAIMER: The information given in this document is believed to be accurate and reliable.
Pin Connection Guidelines Please see the table below on guidelines for connecting all IOs on the Speedster22i HD FPGAs. For completeness, debug I/Os that have no user functionality have also been included and are indicated by a grey background. Pin Name Pin Group Type Description Connection Guidelines 12.
IEEE1149.1 JTAG Interface TMS JTAG Input Test Mode Select (TMS) input controlling the test access port (TAP) controller state machine transitions. This input is captured on the rising edge of the test logic clock (TCK). TCK JTAG Input Dedicated test clock used to advance the TAP controller and clock in data on TDI input and out on TDO output. The maximum frequency for TCK is 100 MHz. TDI JTAG Input Serial input for instruction and test data.
PROGRAM_ENABLE[1:0] CONFIG_DONE CONFIG_CLKSEL CFG CFG CFG Input Input with opendrain or active output Input Pin enabling the programming of the eFuse for the AES encryption keys, which is done in the manufacturing and testing of the devices. These input pins will not be usable by customers. Pin pulled low by FCU prior to the completion of device configuration. After the device successfully completes configuration, this pin is either tri-stated or can optionally be driven high.
CSN[3:0] SD[3:0] CONFIG_SYS_CLK_BYPASS START_CFG_STARTUP 6 CFG CFG CFG CFG Input / Output Input Input Input STAP_SEL CFG Input READ_STATE_ERR CONFIG_SCRUB_MULTIPLE_ERR CFG CFG Output Output command and programming commands are sent via control registers writes done via the IEEE 1149.1 JTAG interface. In the CPU mode, this pin is the bidirectional data bit 0, DQ[0] In SPI Mode: The CSN[3:0] pins are active-low chip select outputs.
feature is used. NOT Available for HD1000. CONFIG_SCRUBBING_ENABLE CFG Input CONFIG_SCRUB_SINGLE_ERR CFG Output Enables SCRUB feature for SEU mitigation in the configuration memory. NOT Available for HD1000. Indicates the presence of a single error when the SCRUB feature is used. NOT Available for HD1000. other devices, connect directly to observation point for error. For the HD1000 tie this pin to GND. For other devices, connect this pin directly to the configuration controller.
Miscellaneous CORE_TESTIN1 EDM DBG DBG Output Output Debug interface used for testing the fabric For factory use / test purposes TEMP_DIODE_P/N TEMP Input Die temperature monitoring diode connections (P and N). EFUSE_PROG EFUSE Output HD1000's EFuse erase / program sequencer controls this signal. This signal should not be touched by user.
Power Analog power supply for the PLLs feeding the FPGA core fabric. CFG Power Supply voltage powering the I/O buffers for the IEEE 1149.1 JTAG interface. The value selected determine the output VOH level on TDO and set the input threshold VIL and VIH values appropriately. (TAP) controller state machine transitions. This input is captured on the rising edge of the test logic clock (TCK).
the FPGA fabric. CFG Power Power Supply for the wordlines of the configuration memory SRAM cells in the FPGA fabric. WVDDA Power Analog Power Supply for FPGA circuitry in the I/O ring. VDD_BRAM VDD_BRAM Power Power Supply for Block RAMS in Fabric. VREF_B[00,01,02,10,11,12,20,21,22, 30, 31,32,40,41,42,50,51,52] VDD_BANK Power Analog input; Voltage Bias reference. Half of corresponding bank / cluster voltage level. Power Bank I/O supply voltage.
Power Supplies and Sequencing Power Supply Block Diagram 12V DC Board Supply Sense line feedback needed for regulator **** Pre-Switching Regulator 0.95V Regulator PA_VDD1 PA_VREG_CMN PA_VREG_RX PA_VREG_SYNTHX 1.0V Regulator VDDL Sense line feedback needed for regulator **** 1.0V Regulator Helps with voltage stability for voltage sensitive supplies VCC VDD_CFG VDD_BRAM VDD_CFGWL** Pre-Switching Regulator 1.0V Regulator Regulator 1.2V / 1.5V / 1.
Power Sequencing Block Diagram Power Up Requirements VCC, VDD_CFG, VDD_BRAM VDD_CFGWL VDDO_B[xx] (1.2V/1.5V/1.8V) VDDO_JCFG AVDD_PLL VDDA_NOM_E/W VCCRAM/FHV_EFUSE PA_VDD1 PA_VDD2 VCC, VDD_CFG, VDD_BRAM VDD_CFGWL VDDO_B[xx] (1.2V/1.5V/1.
Revision History The following table shows the revision history for this document. UG042, August 19, 2014 Date Version 04/05/2013 04/12/2013 04/16/2013 04/29/2013 05/17/2013 06/11/2013 07/26/2013 10/17/2013 11/07/2013 04/24/2014 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 07/17/2014 1.10 08/19/2014 1.11 Revisions Initial Achronix release. Reduced unique power supply requirements. Clarified connection requirements for some SerDes pins. Corrected connection scheme and pull up value (1.
