Owner's manual

The embedded DDR controller macro function performs:
• All required initialization sequences such as the programming of AL and CL values
based on user-defined parameters
• All required calibration algorithms. This includes
 Write levelization
 DQS Enable (to control read-write turnaround of DQ/DQS bi-directional
busses)
 DQS Delay (to skew the DQS by 90 degrees relative to the corresponding
DQ, such that the latter can be sampled in the middle of the bit transition)
• Translation of READ and WRITE requests received from the DDR driver into DDR
protocol i.e. RAS, CAS and WE
• Translation of data to and from SDR to DDR
• Maintaining integrity of memory contents by issuing periodic auto-refresh and zqcal
commands
• Managing the activating and pre-charging of memory banks and rows, as required
• Managing the driving of the memory address pins (with column or row information,
as well as A10 function (precharge-all, auto-precharge, etc)
• Providing a data request signal (‘ddr_int_wrdata_req’) to the DDR driver logic, some
number of cycles after a corresponding write transaction request is received. The
customer logic should be capable of reacting to ddr_int_wrdata_req correctly”. This
ensures that CAS latency, additive latency and burst length are all managed
internally to the Speedster22i DDR controller. It also provides early data request
signal (‘ddr_int_wrdata_req_early’) which can be used if more time is required to
generate data.
• Provides data request signal (‘ddr_int_wrdata_req_align’) and early data request
signal (‘ddr_int_wrdata_req_early_align’) because the wide bus interface or 2X Clock
mode should always be selected for 1866Mpbs.
• Providing a read data valid signal (‘ddr_int_rddata_valid’) to accompany read data
provided in response to a read request. This ensures that the round-trip latency to
(and through) the memory is managed internally to the Speedster22i DDR controller.
It also provides early data valid signal (‘ddr_int_rddata_valid_early’) which can be
used to latch read data.
• Provides data request signal (‘ddr_int_rddata_valid_align’) and early data valid
signal (‘ddr_int_rddata_valid_early_align’) if the wide bus interface or 2X Clock
mode is selected for 1866 Mbps.
• Provide signal (‘ddr_int_busy’) to DDR Driver logic to indicate that the DDR3
Controller is busy and is not accepting new requests.
8 UG031, Nov 18, 2014