Owner's manual

Features
The features supported by the embedded DDR controllers are highlighted below:
• 1866 Mbps data rate
• The controller and PHY can run at 1066 MHz to achieve 1866 Mbps rate at the
memory interface. A 2X Clock setting enables the core to run at half the speed -
533MHz. There is an additional feature to enable a wide bus interface, which
effectively enables the core to run at one quarter the speed - 266MHz. The 2X
clock setting and wide bus interfaces can be enabled at any data rate, thereby
reducing the core frequency by half, or a quarter, respectively.
• 4 Chip Selects per controller
• The external memory connected to each controller can comprise of up to 4 ranks
(either two dual-rank DIMMs or one quad rank DIMM)
• Registered DIMM and Unbuffered DIMM support
• Each controller can independently support either rDIMMs or uDIMMs
• Address mirroring is supported.
• Multi-Burst Mode
• Each controller supports multi-burst mode, up to a burst length of 252 (DDR2) /
254 (DDR) / 248(DDR3). This allows the embedded controller to automatically
issue up to 252 cascaded read or write commands to automatically increment
addresses based on a single command from the Core Fabric
• Backwards Compatible
• The embedded DDR controllers can support DDR3 (up to 1866 Mbps), DDR2 (up
to 800 Mbps) and DDR protocols
• Bypassable
• If the user does not require all six DDR controllers, any (or all) can be bypassed
to leverage use of the designated I/Os for other purposes
• If the user does not require all 72-bits of the data bus, unused byte lanes can be
bypassed to leverage use of the designated I/Os for other purposes
• Minimal LUT use
• The DDR controllers are embedded (hardened), and therefore do not use any of
the LUTs in the core fabric
• LUTs are only required to interface the DDR Controllers
• Zero License fees
6 UG031, Nov 18, 2014