Owner's manual

Figure 12: Read Interface 2X Clock Mode
The following timing diagram illustrates a single read command of burst length 4. The
signals shown in the following diagrams are ports at the (‘ddr3_xSIZE
1
_LOCATION
2
’. Where
1: SIZE = 72, 64, 32, 16, 8 and 2: LOCATION=EN, EC, ES, WN, WC, WS).
Figure 13: Internal Interface Read Protocol Timing Diagram
ddr_
int
_rd
_
request
ddr
_
int_
busy
_
align
ddr_
int_
addr
[33
:0
]
ddr_
int_
rddata
_valid
_
align
ddr
_int
_
rddata[
287:
0
]
Speedster22
i
DDR
Controller
DDR Driver
Logic
(
in Core Fabric)
ddr_
int
_burst
_size
[
7:
0]
ddr_
int
_rddata
_valid
_
early_
align
clk
_div
2
clk
_div
2
ddr
_
int_
rd_
request
a 0
ddr_
int_addr
[33:
0]
ddr_int_busy_align
d0
d1
ddr
_int_ rddata_
valid_align
ddr_int_
rddata[287:0]
Valid Read Command
4
ddr_int_
burst_size[7:0]
Timing relationship between ddr_
int_rd_request and
ddr_int_
rddata_valid assertion based on AL/CL configuration
settings,
refresh status and status of bank/row begins assessed
24 UG031, Nov 18, 2014