Speedster22i DDR3 Controller User Guide UG031 – Nov 18, 2014 UG031, Nov 18, 2014 1
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Table of Contents Table of Figures................................................................................................. 4 Features ............................................................................................................. 6 Introduction ....................................................................................................... 7 Interfaces ...........................................................................................................
Table of Figures Figure 1: Location of Speedster22i DDR Controllers and PHYs ............................................................... 5 Figure 2: Top-level Overview of Embedded DDR Control Logic ............................................................... 7 Figure 3: Address mapping of ‘ddr_int_addr’ Signal ............................................................................... 14 Figure 4: Write Interface 2X Clock Mode .....................................................................
Overview Achronix’s Speedster22i FPGAs contain up to six embedded DDR controllers which can be used to interface with and control off-chip DDR2 or DDR3 memory devices, including DIMMs. Each of the DDR controllers supports up to 72 bits of data and speeds of up to 1866 Mbps. The embedded DDR controllers and PHYs are implemented as Hard-IP blocks in the frame of the Speedster22i FPGAs as illustrated in Figure 1 below.
Features The features supported by the embedded DDR controllers are highlighted below: • 1866 Mbps data rate • • 4 Chip Selects per controller • • • • Each controller can independently support either rDIMMs or uDIMMs • Address mirroring is supported. Multi-Burst Mode • • 6 Each controller supports multi-burst mode, up to a burst length of 252 (DDR2) / 254 (DDR) / 248(DDR3).
Introduction Speedster22i devices contain up to six embedded (Hardened) DDR Controllers. The instantiatable macros for these are called ‘ddr3_xSIZE1_LOCATION2’ where size can be configured as 72,64,32,16 or 8 and location can be EN,EC,ES,WN,WC,WS for a device with six controllers, such as the Speedster22i HD1000. Each Macro is comprised of a DDR Controller and a DDR PHY, and is controlled by the user by means of the DDR driver logic.
The embedded DDR controller macro function performs: 8 • All required initialization sequences such as the programming of AL and CL values based on user-defined parameters • All required calibration algorithms.
Interfaces Internal (core) Interface The internal interface to the PHY/DDR controller, which is implemented in the core fabric, contains the following interface signals as listed below in table 1.
ddr_int_rd_request 1 Input [SIZE*41:0] Output ddr_int_rddata_valid 9 Output ddr_int_rddata_valid_early 9 Output ddr_int_rddata_valid_align 9 Output ddr_int_rddata_valid_early_align 9 Output ddr_int_cmd_auto_pch 1 Input ddr_int_cmd_power_down 2 Input ddr_int_cmd_ref_req 1 Input ddr_int_ref_ack 1 Output ddr_int_cmd_self_referesh 2 Input ddr_int_cmd_zq_cal_req 2 Input ddr_int_zq_cal_ack 1 Output ddr_int_wrdata_valid 1 Output ddr_int_phy_ci_slave_adj ddr_int_phy_ci_slave
External (off-chip) Interface The External DDR interface signals (off-chip) from the DDR PHY to the external memory devices are shown in Table 2 below.
DELAY_READ_TO_PRECHARGE 3'h4 4-6 clock cycles bank Minimum Read to precharge (DDR3 only) DELAY_WRITE_TO_PRECHARGE 4'h8 5-12 clock cycles Minimum time from write to PRECHARGE DELAY_WRITE_TO_READ DELAY_READ_TO_WRITE 3'h4 3'h3 2-6 clock cycles 1-7 clock cycles Minimum time from write to read.
ODT_WRITE_CS0 8'h01 ODT_WRITE_CS1 8'h02 is enabled when set to 1 Each bank contains 8 bits, one per DQ. ODT is enabled when set to 1 Each bank contains 8 bits, one per DQ. ODT is enabled when set to 1 ODT_WRITE_CS2 8'h04 ODT_WRITE_CS3 8'h08 ODT_WRITE_CS4 8’h10 Each bank contains 8 bits, one per DQ. ODT is enabled when set to 1 Each bank contains 8 bits, one per DQ. ODT is enabled when set to 1 Each bank contains 8 bits, one per DQ.
Address Mapping The Speedster22i DDR controller contains a specific address bus mapping which is broken down as follows: • Column [colbits-1:0] • Bank [bankbits-1:0] • Row [rowbits-1:0] • Chip Select (encoded) [3:0] The exact bit positions of the mapping will vary depending on the values of the configuration parameters denoted ‘colbits,’ ‘rowbits,’ and ‘bankbits.
Write Interface Details The Speedster22i DDR controller contains a simple write interface to the DDR Driver logic.. This uses a 2X clock mode - the DDR driving logic (user RTL implemented in the FPGA fabric) runs at half the frequency of DDR controller. The DDR controller/PHY outputs a Clock (‘clk_div2’), which the user must use to drive write data and latch read data.
The following timing diagram illustrates a single write command of burst length 4. The signals shown in the following diagrams are ports at the (‘ddr3_xSIZE1_LOCATION2’. Where 1: SIZE = 72, 64, 32, 16, 8 and 2: LOCATION=EN, EC, ES, WN, WC, WS).
Valid Write commands Present data 1 cycle after ddr_int_wrdata_req_early_align is asserted Clk_div2 ddr_int_wr_ request ddr_int_ addr[33:0] a0 ddr_int_ busy_ align ddr_int_ wrdata_req_ early_ align ddr_int_ wrdata_req d0 ddr_int_ wrdata[287:0] ddr_int_ burst_size[7:0] d1 4 Timing relationship between ddr_int_wr_request assertion and ddr_int_wrdata_req assertion between AL/CWL configurations settings/refresh status, and status of bank/row being accessed Figure 6: Internal Interface Write Proto
clock ACT WR sd_a ROW COL sd_ba BANK BANK sd_cs_n CHIP CHIP Command sd_ras_n sd_cas_n sd_we_n sd_dq d0r d0f d1r d1f d2r d2f d3r d3f sd_dm sd_dqs Notes: For case shown, DELAY_ACTIVATE_TO_RW = 5, CAS WRITE LATENCY =6, DELAY_ADDITIVE_DDR3_LATENCY=0 Figure 7: Write Protocol Timing Diagram (SDRAM Interface) To request a write data transaction, the DDR driver logic (user RTL) must assert ‘ddr_int_wr_request’ along with a corresponding address (‘ddr_int_addr [33:0]’) and burst length (‘ddr_in
Back-to-Back Write Protocol 2X Clock Mode The following timing diagram (Figure 8) illustrates the same three cascaded, back-to-back write commands. Each valid write request (and corresponding data) is highlighted in a different color. For back-to-back write there are 5 clock-cycles gap required between the write requests. This is done with respect to 2X clock mode. Valid Write commands after 5 cycles clk_div2 ... ddr_int_wr_request ... ddr_int_addr[33:0] a0 a1 a2 ddr_int_busy ...
Present data 3-cycles after ddr_int_wrdata_req_early is asserted clk_div2 ... ddr_int_wr_request ... ddr_int_addr[33:0] ddr_int_busy ... ddr_int_wrdata_req_early ...
column address provided by the user for the given write request. For DDR3, since ‘ddr_int_burst_size’ is set as a multiple of 4, the user should always provide a column address with a modulo-8 value. The ‘ddr_int_wrdata [287:0]’ signal represents the data to be written to the memory over two sequential DDR clock edges (144 bits at a time).
ddr_int_wr_request ddr_int_addr[33:0] ddr_int_burst_size[7:0] ddr_int_busy_align DDR Interface Logic (User RTL) Speedster22i DDR Controller ddr_int_wrdata_req_early_align ddr_int_wrdata_req_align ddr_int_wrdata[575:0] ddr_int_writedata_mask[35:0] clk_div4 Figure 10: Write Interface with Wide Bus Interface Enabled The following timing diagram illustrates a single write command of burst length 4. The signals shown in the following diagrams are ports at the (‘ddr3_xSIZE1_LOCATION2’.
As shown above, the wrdata_req signal needs to be asserted for one clock cycle, and in the subsequent clock cycle the write data [575:0] is provided. The timing relationships with the SDRAM interface are essentially equivalent to the 2X Clock Mode interface. A valid write request (ie.
ddr_int_rd_request ddr_int_addr[33:0] ddr_int_burst_size[7:0] ddr_int_busy_align DDR Driver Logic (in Core Fabric) ddr_int_rddata_valid_early_align ddr_int_rddata_valid_align ddr_int_rddata[287:0] Speedster22i DDR Controller clk_div2 Figure 12: Read Interface 2X Clock Mode The following timing diagram illustrates a single read command of burst length 4. The signals shown in the following diagrams are ports at the (‘ddr3_xSIZE1_LOCATION2’.
The Corresponding external (off-chip) interface timing signals are shown in the Figure 14 below.
Valid Write commands after 5 cycles ... clock ... ddr_int_rd_request ddr_int_addr[33:0] a1 a0 a2 ddr_int_busy ... ddr_int_rddata_valid ... ddr_int_rddata [287:0] 4 ddr_int_burst_size [7:0] Figure 15: Read Protocol Timing Diagram (with valid read request highlighted) clock ... ... ddr_int_rd_req ... ... ddr_int_busy ... ... ddr_int_rddata_valid ... ddr_int_addr[33:0] ddr_int_rddata [287:0] ... ...
trip delay of accessing as well as actually reading from the memory address. The read data is accompanied by a valid signal, denoted ‘ddr_int_rddata_valid.
The read requests are subject to the controller being busy (‘ddr_int_busy_align’). The DDR controller supports burst length option BL8. Each burst will contain a single local side transfer, which is equivalent to 8 transfers from the DDR memory.
To request a read data transaction, the DDR driver (user) logic must assert ‘ddr_int_rd_request’ along with a corresponding address (‘ddr_int_addr [33:0]’) and burst length (‘ddr_int_burst_size’). A valid read request (ie.
Memory Interface Latency Depending on the data rate and the mode (width) used, the write and read latency for the DDR3 controller will vary. Table 4 below provides detailed clock cycle counts for write and read latencies for each of these cases.
Customization using ACE Figure 19 below shows the ACE interface which allows customization of the DDR macro. Users can configure the parameter settings according to their requirements and ACE will write out instantiatable RTL, as well as constraint files for use in an ACE project. Figure 19: DDR3 Customization using ACE After setting all parameter values, use the “Generate” button to write out the DDR macro for instantiating into your design.
Revision History The following table shows the revision history for this document. 32 Date Version 3/29/2013 4/15/2013 10/7/14 11/18/14 1.0 1.1 2.0 2.1 Revisions Initial Draft Document Corrected links.
