User Manual

UG027, May 21, 2014
27
FPGA Core
Reset
source
Reset
source
Reset
source
Reset
source
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
8 bit
P
Logic Block
P P P
P P
P
P P P
P P
P
P
P
P
P
P
P
P
P
P
P
P
Logic Block
Logic Block Logic Block
Logic Block Logic Block Logic Block Logic Block
P
P
P
P
P
P
P
P
PP
PP
PP
PP
Programmable
Pipeline
Figure 16: IO Ring Reset Network