ACE User Guide For ACE Version 5.0 UG001 v5.0 - 5th December 2012 http://www.achronix.
Copyright Info Copyright © 2006 - 2012 Achronix Semiconductor Corporation; certain portions of this guide are Copyright © 2000, 2006 IBM Corporation and others. All rights reserved. Achronix and Speedster are trademarks of Achronix Semiconductor Corporation. All other trademarks are the property of their prospective owners. All specifications subject to change without notice. NOTICE of DISCLAIMER: The information given in this document is believed to be accurate and reliable.
CONTENTS CONTENTS Contents 1 Preface 1 1.1 About This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Conventions Used in this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Getting Started 2 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS CONTENTS 3.4.9 Critical Paths View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 3.4.10 Critical Path Diagram View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 3.4.11 Package View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 3.4.12 IO Assignment View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 3.4.13 Clock Regions View . . . . . . . . . . . . . . . . . .
CONTENTS CONTENTS 3.7.5 Multiprocess View Preference Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 3.7.6 Other Colors and Fonts Preference Page . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 3.7.7 Package View Preference Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 3.7.8 Placement Regions Preference Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 3.7.9 Project Management Preference Page . . . . . . . . . . . . . . . .
CONTENTS CONTENTS 4.3.5 Tiling Editors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 4.3.6 Maximizing a View or Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 4.4 Working with Projects and Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 4.4.1 Creating Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 4.4.2 Loading Projects . . . . . . . . . . . . . . . . .
CONTENTS CONTENTS 4.7.2 Setting the IP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 4.7.3 Generating the IP Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 4.7.4 Adding Configuration Files to a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 4.8 4.9 Viewing the Floorplanner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 4.8.1 Opening and Closing the Fly-Out Palette . . .
CONTENTS CONTENTS 4.13.2 Using the SnapShot Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 4.13.3 Setting Up the Bitporter Pod Connection . . . . . . . . . . . . . . . . . . . . . . . . . . 289 4.13.4 Setting Up the Scan Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 4.13.5 Entering a Trigger Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 4.13.6 Configuring Test Stimulus . . . . . . . . . . . . . . . . . . .
CONTENTS CONTENTS 5.13 clear ovals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 5.14 clear polygons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 5.15 clear rectangles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 5.16 clear strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 5.17 clock info . . . . .
CONTENTS CONTENTS 5.53 get extra pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 5.54 get fabricdb path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 5.55 get impl names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 5.56 get impl option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 5.
CONTENTS CONTENTS 5.92 remove path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 5.93 remove project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 5.94 remove project constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 5.95 remove project ip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 5.96 remove project netlist . .
CONTENTS CONTENTS 5.131save place and route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 5.131.1 Usage Notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 5.132save placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 5.133save impl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 5.133.1 Usage Notes: . . . . . . . . .
Conventions Used in this Guide Chapter 1. Preface Preface About This Guide This guide is a reference manual for the Achronix CAD Environment (ACE), used for placing, routing, configuring, and debugging Achronix FPGAs. ACE works in conjunction with 3rd Party Synthesis and Simulation tools to provide a complete design environment for Achronix FPGAs. This guide consists of the following chapters: Getting Started includes an Introduction to ACE and a quick Tutorial.
Chapter 2. Getting Started Getting Started Introduction The Achronix implementation flow uses an industry standard RTL synthesis flow based on Synplify-Pro from Synplicity and Precision Synthesis from Mentor Graphics. Working in conjunction with the synthesis tool, Achronix CAD Environment (ACE) provides • Placement • Routing • Timing Analysis • Bitstream Generation • FPGA Configuration • On-chip Debugging UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
ACE Quickstart Tutorial Chapter 2. Getting Started ACE Quickstart Tutorial Start by copying all the files from /Achronix/examples/quickstart into a new empty directory (). Now click the ( simple steps to complete your first design in ACE. ) icon in the upper right corner. Then follow these 1. Create your Project In the Projects view, click the Create Project ( ) toolbar button.
Perspectives Chapter 3. Concepts Concepts Workbench The term Workbench refers to the desktop development environment within ACE. The Workbench aims to achieve seamless tool integration and controlled openness by providing a common platform for the creation, management, and navigation of workspace resources. Each Workbench window contains one or more perspectives. Perspectives contain views and editors and control what appears in certain menus and tool bars.
Perspectives Chapter 3. Concepts By default, this perspective contains the ”Projects View”, ”IP Libraries View”, ”IP Diagram View”, ”IP Problems View”, ”Outline View”, ”TCL Console View”, and the Editor Area, which can contain any ACE Editor or Report. See Creating an IP Configuration for more details. Bitporter Perspective The Bitporter Perspective allows interaction with Achronix FPGAs via JTAG through a Bitporter pod. Downloading the device configuration and debugging will typically happen from here.
Editors Chapter 3. Concepts Editors Most perspectives in the Workbench are comprised of an editor area and one or more views. Different editors are associated with different types of files. For example, when a file is opened by double-clicking for editing in the Projects View, the associated editor opens in the Workbench. If there is no associated editor for a resource, the Workbench attempts to launch an external editor outside the Workbench.
Editors Chapter 3. Concepts HTML Report Browser When HTML versions of generated Reports are opened within ACE, they are displayed within the Editor area using the HTML Report Browser. This is a very limited form of a web browser - it only allows hyperlink traversal, refresh, forward, and back operations. Note: The HTML Report Browser should typically not be used to browse the Internet - a dedicated web browser like Firefox would be a much better choice for both security and performance reasons.
Editors Chapter 3. Concepts Advanced PLL Configuration Editor The Advanced PLL Configuration Editor provides a graphical wizard for creating a PLL configuration file (.acxip). This editor allows the user to generate the required configuration files for design with the embedded PLLs. See Creating an IP Configuration. Unlike the much simpler Basic PLL Configuration Editor, the Advanced PLL Configuration Editor allows the user to access the complete functionality of the PLL.
Editors Chapter 3. Concepts Overview Page The Overview page contains the top-level, global properties that govern the structure and base configuration of the PLL. Changes made on this page affect all the outputs for this PLL. Figure 3.3: Advanced PLL IP Editor Overview Page 9 http://www.achronix.com UG001 Rev. 5.
Editors Chapter 3. Concepts PLL Editor Overview Page Options Option Editable Description Target Device Y The Speedster22i device this PLL is intended to target. Refclk Input Frequency (MHz) Y The frequency of the PLL reference clock input. Number of Desired Clock Outputs Y The number of desired clock output signals for this PLL. Changing this will alter the number of active pages of Clock Output configuration options.
Editors Chapter 3. Concepts This calculated value shows the exact ”Feedback Divider ’NF’” value which will be used by the PLL. This may differ slightly from the requested value; the closest approximate value will be chosen if an exact match is not possible. Achieved NF Clkout Driving External Feedback Path Y Selects which of the currently-enabled clock outputs will drive the external feedback path. Note that Phase Adjustment is not allowed in the Feedback Path.
Editors Chapter 3. Concepts Placement Page The Placement page contains configuration information relating to the PLLs placement in the Speedster device. The site chosen will be exported in a placement constraints (.pdc) file when the user chooses to generate their PLL design files. Figure 3.4: Advanced PLL IP Editor Placement Page PLL Editor Placement Page Options Option Editable Description Site Corner Y The corner of the Speedster22i device where this PLL instance should be placed.
Editors Chapter 3. Concepts Clock Output [0,1,2,3] Pages The Clock Output pages each contain general configuration information relating to a single PLL output signal. Since there are one-to-four PLL output signals per PLL (as configured on the Overview Page), between one and four Clock Output pages will be enabled. Figure 3.
Editors Chapter 3. Concepts Output Divider [0,1,2,3] Pages The Output Divider pages contain configuration information relating to the output divider (OD) of one of the PLLs clock output signals. Since there are one-to-four PLL output signals per PLL, there are also up to four of these pages. Because the PLL and OD logic may be bypassed on a per-output basis (as configured on the Clock Output [0,1,2,3] Pages), this page may sometimes be hidden, even if the related clock output is enabled. Figure 3.
Editors Chapter 3. Concepts OD [0,1,2,3] Phase Adjustment Pages The Output Divider (OD) Phase Adjustment pages contain configuration information about the potential phase adjustment performed in an OD for one of the PLLs clkout signals. This page will only be visible when the associated Output Divider [0,1,2,3] Pages are enabled, and the setting ”Enable OD[0-3] Phase Adjustment” is selected.
Editors Chapter 3. Concepts PLL Editor OD Phase Adjustment Options Option Editable OD[0-3] Phase Shift Increment Unit Description The incremental step, always 45 degrees, by which the OD output signal will be shifted relative to the VCO output signal. This is a fixed value, displayed for user convenience. Static Adjustment Y When selected, a single, unchanging phase adjustment must be chosen for this OD. When this is enabled, the ”Phase Adjustment Multiplier” field will also be enabled.
Editors Chapter 3. Concepts Output Synthesizer [0,1,2,3] Pages The Output Synthesizer (OS) pages contain configuration information relating to the OS associated with the PLLs selected clock output. Because the OS can be disabled for a PLL clock output, this page is only visible when the ”Enable Output Synthesizer (OS[0-3])” field on the appropriate Clock Output [0,1,2,3] Page is enabled. Figure 3.
Editors Chapter 3. Concepts Port Names Page The Port Names page contains all the input and output ports which will be used by the PLL in its current configuration. (Changing options on other pages will show and hide port names on this page, as the need for the ports changes.) Figure 3.9: IP Advanced PLL Editor Port Names Page NOTE: All port names entered on this page must adhere to Verilog and VHDL naming standards. Illegal names will be caught as errors, and will prohibit RTL wrapper file generation.
Editors Chapter 3. Concepts Advanced PLL Editor Port Names Page Options Option Description Input Ports Name for Input ”refclk” The desired name for the reference clock input signal in the generated RTL. Name for Input ”fbclk” The desired name for the feedback clock input signal in the generated RTL. This option is not available when the PLL is in Pure Internal Feedback Mode.
Editors Chapter 3. Concepts Basic PLL Configuration Editor The Basic PLL Configuration Editor provides a simplified graphical wizard for creating a PLL configuration file (.acxip). This editor allows the user to generate the required configuration files for design with the embedded PLLs. See Creating an IP Configuration. Unlike the much more complicated Advanced PLL Configuration Editor, the Basic PLL Configuration Editor allows the user to access only the most-often used functionality of the PLL.
Editors Chapter 3. Concepts Overview Page The Overview page contains all the properties that govern the structure and configuration of the basic PLL. Figure 3.11: Basic PLL IP Editor Overview Page PLL Editor Overview Page Options Option Editable Description Target Device Y The Speedster22i device this PLL is intended to target. Number of Desired Clock Outputs Y The number of desired clock output signals for this PLL.
Editors clkout0 Desired Frequency Chapter 3. Concepts Y clkout0 Achieved Frequency The frequency desired for clkout0. ACE will automatically choose PLL configuration values (NR, NF, OD0, OS0) to get as close to the desired frequency as possible. The calculated output frequency of the clkout0 clock output signal. This will be as close to the ”clkout0 Desired Frequency” as possible. VCO Frequency The calculated VCO output frequency which was required to achieve the requested clkout0 frequency.
Editors Chapter 3. Concepts BRAM Configuration Editor The BRAM Configuration Editor provides a simplified graphical wizard for creating a BRAM configuration file (.acxip). This editor allows the user to generate the required configuration files for design with the embedded PLLs. See Creating an IP Configuration. By default, the BRAM Configuration Editor is included in the IP Configuration perspective (Window→Open Perspective→IP Configuration) ( ).
Editors Chapter 3. Concepts Overview Page The Overview page contains all the properties that govern the structure and configuration of the BRAM wrapper. BRAM Editor Overview Page Options Option Editable Description Port A Configuration Y BRAMs can be configured for read, write, or read/write capability independently on both Port A and Port B sides of the BRAM. Data Width Y Port A side write and read port data width.
Editors Chapter 3. Concepts Clock Enable Priority Y The Clock Enable Priority defines the priority of the outregcea clock enable input relative to the rstrega reset input during an assertion of the rstrega signal on the output register of Port A. The value rstreg allows the Port A output register to be set/reset at the next active edge of the Port A clock without requiring a specific value on the outregcea output register clock enable input.
Editors Chapter 3. Concepts Output Register Clock Enable Priority Y The Clock Enable Priority defines the priority of the outregceb clock enable input relative to the rstregb reset input during an assertion of the rstregb signal on the output register of Port B. The value rstreg allows the Port B output register to be set/reset at the next active edge of the Port B clock without requiring a specific value on the outregceb output register clock enable input.
Editors Chapter 3. Concepts Figure 3.13: BRAM IP Editor Overview Page 27 http://www.achronix.com UG001 Rev. 5.
Editors Chapter 3. Concepts DDR3 Configuration Editor The DDR3 Configuration Editor provides a graphical wizard for creating a DDR3 Interface IP configuration file (.acxip). This editor allows the user to generate the required configuration files for designs requiring the embedded DDR3 controllers. See Creating an IP Configuration. By default, the DDR3 Configuration Editor is included in the IP Configuration perspective (Window→Open Perspective→IP Configuration) ( ).
Editors Chapter 3. Concepts Figure 3.14: A Module diagram for DDR3 in the IP Diagram View 29 http://www.achronix.com UG001 Rev. 5.
Editors Chapter 3. Concepts Figure 3.15: A Placement diagram for DDR3 in the IP Diagram View. UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts Overview Page The Overview page contains the top-level, global properties that govern the structure and base configuration of the DDR3 Interface. Figure 3.16: DDR3 IP Editor Overview Page 31 http://www.achronix.com UG001 Rev. 5.
Editors Chapter 3. Concepts DDR3 Editor Overview Page Options Option Description Target Device Allows the user to select from the Achronix devices that support this IP. Placement Select the location on the chip where this DDR interface should be placed. Clock Pin Name Enter the reference clock pin name. Will be used to generate clock constraints. May be a top level design pin, a PLL clock output pin, etc.
Editors Chapter 3. Concepts Memory Timing Page The Memory Timing Page allows the user to configure the memory timings for the DDR3 Interface.
Editors Chapter 3. Concepts Figure 3.17: DDR3 IP Editor Memory Timing Page UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts DLL Timing Page The DLL Timing Page allows the user to configure the DLL timing parameters for the DDR3 Interface.
Editors Chapter 3. Concepts Figure 3.18: DDR3 IP Editor DLL Timing Page UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts On-Die Termination Page The On-Die Termination Page allows the user to configure the On-Die Termination parameters for the DDR3 Interface. Figure 3.19: DDR3 IP Editor On-Die Termination Page 37 http://www.achronix.com UG001 Rev. 5.
Editors Chapter 3. Concepts DDR3 Editor On-Die Termination Page Options Option Description ODT Selection for Reads ODT Read CS0 Enable/Disable On-Die Termination for READS on Chip Select 0 ODT Read CS1 Enable/Disable On-Die Termination for READS on Chip Select 1 ... ...
Editors Chapter 3. Concepts Ethernet Configuration Editor The Ethernet interface configuration editor provides a simple graphical editor used to configure the SerDes interface for the Ethernet protocol, and saves the user configuration in an Ethernet IP configuration file (.acxip). See Creating an IP Configuration. By default, the Ethernet Configuration Editor is included in the IP Configuration perspective (Window→Open Perspective→IP Configuration) ( ).
Editors Chapter 3. Concepts Figure 3.21: Ethernet IP Editor Module Diagram UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts Overview Page The Overview page of the Ethernet IP Configuration Editor contains all the options that govern the structure and configuration of the Ethernet interface. Figure 3.22: Ethernet IP Editor Overview Page 41 http://www.achronix.com UG001 Rev. 5.
Editors Chapter 3. Concepts Ethernet Editor Overview Page Options Option Description Target Device Select the intended 22i Target Device. This may affect choices in other option fields, and will affect the generated wrapper files. Lane Configuration and Placement Lane Configuration Use this field to select the placement of each lane interface with respect to the MAC. 100G consumes a block of 10 serdes lanes, 40G consumes a block of 4 serdes lanes, and 10G consumes a single serdes lane.
Editors Chapter 3. Concepts FIFO Configuration Editor The FIFO Configuration Editor provides a graphical wizard for creating a FIFO configuration file (.acxip). This editor allows the user to generate the required configuration files for design with the embedded BRAMs. See Creating an IP Configuration. By default, the FIFO Configuration Editor is included in the IP Configuration perspective (Window→Open Perspective→IP Configuration) ( ).
Editors Chapter 3. Concepts Overview Page The Overview page contains the top-level, global properties that govern the structure and base configuration of the FIFO. FIFO Editor Overview Page Options Option Editable Description Clock Mode Y FIFOs can be configured in Single Clock mode to use a single clock domain for writes and reads. Single clock mode bypasses the synchronization circuitry to enable faster updates to status flags.
Editors Chapter 3. Concepts Y The Clock Enable Priority controls the relationship between the outregce clock enable input and the rstreg reset input during an assertion of the rstreg signal on the output register. Setting the value to rstreg allows the output register to be set/reset at the next active edge of the rdclk without requiring a specific value on the outregce output register clock enable input.
Editors Chapter 3. Concepts Read Pointer Sync Stage Depth Y The rdptr sync stages parameter defines the number of stages used in the Read Pointer Synchonizer circuit that synchronizes the Read Pointer to the wrclk clock domain. When the FIFO is in Dual Clock mode, the output of the synchonized Read Pointer is compared to the Write Pointer to generate the empty and almost empty flags. Write Enable Active-High Y When this is enabled, the write enable (wren) pin is an active-high.
Editors Chapter 3. Concepts Figure 3.24: FIFO IP Editor Overview Page 47 http://www.achronix.com UG001 Rev. 5.
Editors Chapter 3. Concepts Reset Configuration Page The Reset Configuration page contains the properties that govern the reset behavior of the FIFO. Figure 3.25: FIFO IP Editor Reset Configuration Page FIFO Editor Reset Configuration Page Options Option Editable Description Enable Advanced Reset Mode Y When this is enabled, both the read and write port reset signals are exposed separately and the user can configure the advanced reset input mode and synchronization register stages.
Editors Chapter 3. Concepts Write Pointer Reset Source Y The Write Pointer Reset Source selects the reset source for the write pointer by configuring the wrrst input mode parameter on the FIFO. The FIFO macro provides the user with several options to reset the FIFO either sychronously or to synchronize the reset input to the appropriate clock domain within the FIFO without the need to implement separate synchronization circuitry in the FPGA fabric.
Editors Chapter 3. Concepts Interlaken Configuration Editor The Interlaken interface configuration editor provides a simple graphical editor used to configure the SerDes interface for Interlaken, and saves the user configuration in an Interlaken IP configuration file (.acxip). See Creating an IP Configuration.
Editors Chapter 3. Concepts Figure 3.27: Interlaken IP Module Diagram for a six-lane instance 51 http://www.achronix.com UG001 Rev. 5.
Editors Chapter 3. Concepts Overview Page The Overview page contains the top-level, global options that govern the structure and base configuration of the Interlaken interface wrapper. Figure 3.28: Interlaken IP Editor Overview Page Interlaken Editor Overview Page Options Option Editable Description Number of Lanes Y Sets the number of lanes to be exposed in the RTL wrapper. Tx Data Rate (Gbps) Y Desired transmit-side data rate for the SerDes. The Rx Data Rate will match this value.
Editors Number of Channels Chapter 3. Concepts Y The number of channels to be used. Y Selects which Interlaken site will be used for placement. (See the Placement IP Diagram.) Placement Interlaken Block 53 http://www.achronix.com UG001 Rev. 5.
Editors Chapter 3. Concepts Rx PMA Equalization Page This page allows the customization of the PMA equalization settings of the Interlaken wrapper. Figure 3.29: Rx PMA Equalization Page – Interlaken Configuration Editor Rx PMA Equalization Page Options Options Description Automatically Calibrate When enabled, automatically calibrates the Receiver Settings (and disables the fields.) When disabled, the user is allowed to configure the Receiver Settings.
Editors DFE Pulse-shaping Tap 3dB Freq DFE pulse-shaping tap 3dB frequency DFE Pulse-shaping Tab Gain DFE pulse-shaping tap gain DFE N1 Tap Gain Control (mV) DFE tap 1 gain control DFE N2 Tap Gain Control (mV) DFE tap 2 gain control DFE N3 Tap Gain Control (mV) DFE tap 3 gain control DFE N4 Tap Gain Control (mV) DFE tap 4 gain control Rx User Control from Fabric 55 Chapter 3. Concepts Control Rx PMA settings from user logic with chX i pma rxeqlut[32:0] and chX i pma rxeqlut str. http://www.
Editors Chapter 3. Concepts Rx PMA PLL Page This page allows customization of the Rx PLL settings of the Interlaken wrapper. Figure 3.30: Rx PMA PLL Page – Interlaken Configuration Editor Rx PMA PLL Page Options Option Description Rx PPM When Rx PLL is within this PPM range PMA will consider Tx PLL to be locked UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts Tx PMA Driver Page This page allows the customization of the Tx PMA Driver settings for the Interlaken wrapper. Figure 3.31: Tx PMA Driver Page – Interlaken Configuration Editor Tx PMA Driver Page Options Option Editable Description Transmit Amplitude (mVdiff-pkpk) Y Defines the full-scale maximum swing of the driver Cursor Level N Y Defines the total number of driver units allocated to the sum of the driver taps.
Editors Chapter 3. Concepts Transition Bit Amplitude (mV) ((Cursor Level)+3)/34*(Transmit Amplitude) Postcursor Bit Amplitude (mV) ((Cursor Level)+3-2*(Post-Cursor Level))/34*(Transmit Amplitude) De-emphasis Level (dB) LOG10((Post-Cursor Level)/(Cursor Level))*20 UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts Tx PMA PLL Page This page allows the customization of the Tx PMA PLL settings for the Interlaken wrapper. Figure 3.32: Tx PMA PLL Page – Interlaken Configuration Editor Tx PMA PLL Settings Page Options Option Description Tx PPM When Tx PLL is within this PPM range PMA will consider Tx PLL to be locked Enable Spread Spectrum Enables spread-spectrum clock for this transmitter. Spread Spectrum 59 Frequency (kHz) Sets the spread-spectrum frequency.
Editors Chapter 3. Concepts Interrupt Settings Page This page allows the customization of the Interrupts for the Interlaken wrapper. Figure 3.33: Interrupt Settings Page – Interlaken Configuration Editor UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts Interrupt Settings Page Options Option Description Enable Master Interrupt Override Allows the use of the Master Interrupt Override. Master Interrupt Override Value If enabled, this value is transmitted to the INT signal. Word Synchronization Interrupts Lane 0 Enables the word synchronization interrupt for lane 0. ... ... Lane 11 Enables the word synchronization interrupt for lane 11.
Editors Chapter 3. Concepts Interlaken Tx Settings Page This page contains the Interlaken Transmit-side settings for the Interlaken wrapper. Figure 3.34: Interlaken Tx Settings Page – Interlaken IP Configuration Editor Interlaken Tx Settings Options Option Description Enable TX LBUS Ready Threshold TX LBUS Ready Threshold TX Decommissioning Register UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts TX Has Bad Lane TX Bad Lane TX Last Lane TX Rate Limiter Enable TX Rate Limiter Max Tokens (hex) Specifies how many tokens are to be added to the token bucket after each interval. This value must be greater than 0. This value should not be changed when the rate limiter is enabled. Delta (hex) Specifies how many tokens are to be added to the token bucket after each interval. This value must be greater than 0. This value should not be changed when the rate limiter is enabled.
Editors Chapter 3. Concepts Interlaken Rx Settings Page This page configures the Interlaken Receive-side settings for the Interlaken wrapper. Figure 3.35: Interlaken Rx Settings Page – Interlaken IP Configuration Editor Interlaken Rx Settings Page Options Option Description RX Decommissioning Register RX Has Bad Lane RX Bad Lane RX Last Lane RX Meta Frame Length (hex) UG001 Rev. 5.0 - 5th December 2012 This input should be -1 the desired length.
Editors Chapter 3. Concepts RX Packet Mode Changes the way the error handler reports errors. Either packets are expected to arrive interwoven as segments, or packets are expected to arrive as complete packets. This setting ensures that packets delivered to the Local bus had the appropriate SOP and EOP pairing. RX Maximum Burst Control Word Spacing Specifies the maximum number of Data Words between Burst Control Words expected by the RX. 65 http://www.achronix.com UG001 Rev. 5.
Editors Chapter 3. Concepts LRAM Configuration Editor The LRAM Configuration Editor provides a simplified graphical wizard for creating an LRAM wrapper IP configuration file (.acxip). This editor allows the user to generate the required configuration files for design with the embedded LRAM. See Creating an IP Configuration. By default, the LRAM Configuration Editor is included in the IP Configuration perspective (Window→Open Perspective→IP Configuration) ( ).
Editors Chapter 3. Concepts Overview Page The Overview page contains all the properties that govern the structure and configuration of the LRAM wrapper. Figure 3.37: LRAM IP Editor Overview Page LRAM Editor Overview Page Options Option Editable Description Data Width Y Data width of read and write ports. Address Depth Y Desired address depth of the LRAM. Read Clock Polarity Y The read port clock polarity can be set to use either rising edge assignment or falling edge assignment.
Editors Chapter 3. Concepts Write Clock Polarity Y The write port clock polarity can be set to use either rising edge assignment or falling edge assignment. Output Register Enabled Y When the Output Register is enabled, there is an additional cycle of latency for each read operation. Y The Clock Enable Priority defines the priority of the outregce clock enable input relative to the rstreg reset input during an assertion of the rstreg signal on the read port output register.
Editors Chapter 3. Concepts LRAM FIFO Configuration Editor The LRAM FIFO Configuration Editor provides a graphical wizard for creating an LRAM FIFO configuration file (.acxip). This editor allows the user to generate the required configuration files for design with the embedded LRAMs. See Creating an IP Configuration. By default, the LRAM FIFO Configuration Editor is included in the IP Configuration perspective (Window→Open Perspective→IP Configuration) ( ).
Editors Chapter 3. Concepts Overview Page The Overview page contains the top-level, global properties that govern the structure and base configuration of the LRAM FIFO. Figure 3.39: LRAM FIFO IP Editor Overview Page LRAM FIFO Editor Overview Page Options Option Description Clock Mode FIFOs can be configured in Single Clock mode to use a single clock domain for writes and reads. Single clock mode bypasses the synchronization circuitry to enable faster updates to status flags.
Editors Chapter 3. Concepts Almost Full Offset (decimal) This defines the word depth at which the FIFO almost full signal is asserted. The almost full flag is asserted when there are (afull offset + 1) or fewer locations available to be written in the FIFO. The almost full signal is asserted when the the difference between the Write Pointer and the Read Pointer is greater than or equal to the difference between the Maximum FIFO Depth and the value of this field (afull offset parameter).
Editors Chapter 3. Concepts PCI Express Configuration Editor The PCI Express (PCIe) interface configuration editor provides a simple graphical editor used to configure the SerDes interface for PCIe, and saves the user configuration in a PCIe IP configuration file (.acxip). See Creating an IP Configuration.
Editors Chapter 3. Concepts Figure 3.41: PCIe IP Module Diagram 73 http://www.achronix.com UG001 Rev. 5.
Editors Chapter 3. Concepts Overview Page The Overview page contains all the options that govern the structure and configuration of the PCI Express interface. Figure 3.42: PCIe IP Editor Overview Page PCIe Editor Overview Page Options Option Description Target Device The Target Device allows you to select from any compatible Speedster22i devices for placing the PCI Express core and SerDes lanes.
Editors Chapter 3. Concepts PCIe Placement Choose which site this PCIe instance should occupy. The Placement IP Diagram will be updated to show the chosen configuration. Device ID (hex) The PCI Express Device ID Revision ID (hex) The PCI Express Revision ID Subsystem ID (hex) The PCI Express Sub-system ID Vendor ID (hex) The PCI Express Vendor ID Subsystem Vendor ID (hex) The PCI Express Subsystem Vendor ID Class Code (hex) Value returned when the Class Code Configuration Register is read.
Editors Chapter 3. Concepts Memory Map Page This page contains the options that pertain to the PCIe Memory Map. Figure 3.43: PCIe IP Editor Memory Map Page UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts PCIe Editor Overview Page Options Option Description BAR0 BAR0 Type Each BAR can be configured as Memory or I/O BAR0 Width Each BAR can be configured as 32-bit or 64-bit BAR0 Size The size of the BAR in bytes.
Editors Chapter 3. Concepts Power Management Page This page contains all the options for PCIe power management. Figure 3.44: PCIe IP Editor Power Management Page PCIe Editor Power Management Page Options Option Description NTFS (hex) Number of NFTS sets to request when exiting L0s. This is the NFTS value transmitted in TS1 and TS2 Ordered Sets during training. L0s Tx Entry Time (hex) Number of nanoseconds of idle time to wait before entering L0s TX.
Editors Chapter 3. Concepts Enable L1 ASPM Support Active State Power Management (ASPM) Support L1 Entry Time (hex) Number of microseconds of idle time to wait before requesting entry to ASPM L1 (used by Upstream Ports Endpoint/Upstream Switch - only). Idle time is defined as no TLP or ACK/NAK DLLP transmissions. PCIe Specification does not define a minimum or maximum value. Too low a value risks wasting link bandwidth due to ASPM L1 entry/exit latencies.
Editors Chapter 3. Concepts Advanced Features Page This page contains all the options that govern the advanced features of the PCI Express interface. Figure 3.45: PCIe IP Editor Advanced Features Page PCIe Editor Advanced Features Page Options Option Description Extended Tag Field Supported Enable Extended Tag Field Support Maximum Payload Size Sets the maximum payload size supported UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts Phantom Functions Support Phantom Function support for the Function must be enabled by the Phantom Functions Enable field in the Device Control register before the Function is permitted to use the Function Number field in the Requester ID for Phantom Functions. If Phantom Functions Supported != 00, the core implements the Phantom Functions Enable register as read/write resetting to 0 and otherwise implements Phantom Functions Enable as read only tied to 0.
Editors MSI-X PBA Offset (hex) Chapter 3. Concepts Same as MSI-X Table Offset, but indicates the Base Address Register offset for the MSI-X PBA rather than the MSI-X Table UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts Gen 3 Equalization Page This page contains all the options that govern Gen 3 PCI Express equalization. PCIe Editor Gen 3 Equalization Page Options Option Description Equalization Method The Equalization method to use: Preset, Algorithm, or Table Equalization TS1 Ack Delay Defines how long the upstream port (Phase 2) or downstream port (Phase 3) waits after requesting new coefficients/presets before looking for incoming EQ TS1 sets from the remote link partner.
Editors Chapter 3. Concepts Figure 3.46: PCIe IP Editor Gen 3 Equalization Page UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts ROM Configuration Editor The ROM configuration editor provides a simple graphical editor used to configure a ROM wrapper instance, and saves the user configuration in a ROM IP configuration file (.acxip). See Creating an IP Configuration.
Editors Chapter 3. Concepts Overview Page The Overview page contains all the properties that govern the structure and configuration of the ROM wrapper. Figure 3.48: ROM IP Editor Overview Page ROM Editor Overview Page Options Option Description RAM Type The ROM can be built out of Block RAMs or Logic RAMs. Data Width Data width of the read port. Address Depth Desired address depth of the ROM.
Editors Clock Enable Priority Memory Initialization File 87 Chapter 3. Concepts The Clock Enable Priority defines the priority of the outregce clock enable input relative to the rstreg reset input during an assertion of the rstreg signal on the read port output register. Setting this field to rstreg allows the output register to be set/reset at the next active edge of the read port clock without requiring a specific value on the outregce output register clock enable input.
Editors Chapter 3. Concepts SerDes Configuration Editor The SerDes Configuration Editor provides a graphical wizard for creating a SerDes IP configuration file (.acxip). This view allows the user to generate the required configuration files for design with the embedded 12G SerDes. Pages are accessed via Back and Next buttons. By default, the SerDes Configuration Editor is included in the IP Configuration Perspective (Window → Open Perspective → IP Configuration).
Editors NOTE: Chapter 3. Concepts Lanes which are not available in the current package/configuration will be grey (disabled) in the diagram. Module Diagram The Module Diagram shows the inputs and outputs of the SerDes instance currently being configured in the Editor. 89 http://www.achronix.com UG001 Rev. 5.
Editors Chapter 3. Concepts Figure 3.50: Module Diagram – SerDes Configuration Editor UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts Overview Page This Overview page contains the top-level, global properties that govern the structure and base configuration of the 12G SerDes wrapper. Figure 3.51: Overview Page – SerDes Configuration Editor 91 http://www.achronix.com UG001 Rev. 5.
Editors Chapter 3. Concepts Overview Page Options Option Description Standard Specifies the transmission standard to be used.(1) Number of Lanes Sets the number of lanes to be used. Tx Data Rate (Gbps) Desired transmit-side data rate. Rx Data Rate (Gbps) Sets the receive-side data rate. Ref Clock (MHz) Sets the reference clock. Rx Termination (ohms) Rx Lane calibration impedance setting Tx Termination (ohms) Tx Lane calibration impedance setting Data Width Data width to the SerDes.
Editors Chapter 3. Concepts PMA Settings Page Allows the user to select a uniform or lane-based PMA. Figure 3.52: PMA Settings Page – SerDes Configuration Editor PMA Settings Page Options Option Description Enable lane-specific Rx PMA Settings If enabled, instead of a single page configuring the Rx PMA settings for all lanes, each lane will have its own page.
Editors Chapter 3. Concepts Rx PMA Equalization Pages These pages allow the customization of the PMA equalization settings of the SerDes. Depending upon whether ”Enable lane-specific Rx PMA Settings” is selected on the PMA Settings page, there will be either a single page configuring all lanes, or an individual page for each lane. Each page will have identical settings available to the user. Figure 3.
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Editors Chapter 3. Concepts Rx PMA PLL Page This page allows customization of the Rx PLL settings of the SerDes. Depending upon the setting of ”Enable lane-specific Rx PMA PLL Settings” on the PMA Settings page, either a single page is provided to configure all lanes, or an individual page is provided for each lane. Regardless of the page title, the available settings are identical. Figure 3.
Editors Chapter 3. Concepts Tx PMA Driver Page This page allows the customization of the Tx PMA Driver settings for the SerDes. Depending upon whether the option ”Enable lane-specific Tx PMA Driver Settings” is selected on the PMA Settings page, one or more pages with identical available settings will be provided. Figure 3.
Editors Tx User Control from Fabric Chapter 3. Concepts Y Control PMA Transmit de-emphasis from fabric Precursor Bit Amplitude (mV) ((Cursor Level)+3-2*(Pre-Cursor Level))/34*(Transmit Amplitude) Transition Bit Amplitude (mV) ((Cursor Level)+3)/34*(Transmit Amplitude) Postcursor Bit Amplitude (mV) ((Cursor Level)+3-2*(Post-Cursor Level))/34*(Transmit Amplitude) De-emphasis Level (dB) LOG10((Post-Cursor Level)/(Cursor Level))*20 UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts Tx PMA PLL Page This page allows the customization of the Tx PMA PLL settings for the SerDes. Depending upon whether the option ”Enable lane-specific Tx PMA PLL Settings” is selected on the PMA Settings page, one or more pages with identical available settings will be provided. Figure 3.
Editors Chapter 3. Concepts PCS Settings Page The PCS Settings page allows the user to configure the granularity level of Tx/Rx physical coding sublayer (PCS) customization. Figure 3.57: PCS Settings Page PCS Settings Page Options Option Description Enable lane-specific Rx PCS Settings If enabled, instead of a single page configuring the Rx PCS settings and a single page configuring Rx PCS Symbol Alignment for all lanes, each lane will have its own pages.
Editors Chapter 3. Concepts Rx PCS Settings Page These pages allow the customization of the Rx PCS settings of the SerDes. Depending upon whether ”Enable lane-specific Rx PCS Settings” is selected on the PCS Settings page, there will be either a single page configuring all lanes, or an individual page for each lane. Each page will have identical settings available to the user. Figure 3.58: Rx PCS Settings Page – SerDes Configuration Editor 101 http://www.achronix.com UG001 Rev. 5.
Editors Chapter 3. Concepts Rx PCS Settings Page Options Option Description Decoder PCS Decoder Selection Receive Symbol Swap Swap upper word and lower word if in 16 or 20-bit mode Receive Bit Order Reverse Reverse bit order within each word Receive Polarity Reverse Reverse polarity for all bits Elastic FIFO Use Elastic FIFO Enable elastic FIFO 8B Mode Elastic FIFO to operate in 8-bit mode SKIP Mode Specify elastic fifo mode of operation.
Editors Chapter 3. Concepts Rx PCS Symbol Alignment Page These pages allow the customization of the Rx PCS Symbol Alignment settings of the SerDes. Depending upon whether ”Enable lane-specific Rx PCS Settings” is selected on the PCS Settings page, there will be either a single page configuring all lanes, or an individual page for each lane. Each page will have identical settings available to the user. Figure 3.59: Rx PCS Symbol Alignment Page – SerDes Configuration Editor 103 http://www.achronix.
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Editors Chapter 3. Concepts Tx PCS Settings Page These pages allow the customization of the Tx PCS settings of the SerDes. Depending upon whether ”Enable lane-specific Tx PCS Settings” is selected on the PCS Settings page, there will be either a single page configuring all lanes, or an individual page for each lane. Each page will have identical settings available to the user. Figure 3.
Editors Chapter 3. Concepts Channel Bonding Page This page allows the customization of the Channel Bonding settings of the SerDes. Figure 3.61: Channel Bonding Page – SerDes Configuration Editor UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts Channel Bonding Settings Page Options Option Description Deskew Mode Deskew operation mode: automatic, manual, or bit-slip.
Editors Chapter 3. Concepts Deskew Word 3 Deskew Sequence 1 word 3 Enable Alt 3 Enable deskew sequence 1 alternate word 3 Deskew Alt 3 Deskew Sequence 1 Alternate word 3 Deskew Word 4 Deskew Sequence 1 word 4 Enable Alt 4 Enable deskew sequence 1 alternate word 4 Deskew Alt 4 Deskew Sequence 1 Alternate word 4 Deskew Word 5 Deskew Sequence 1 word 5 Enable Alt 5 Enable deskew sequence 1 alternate word 5 Deskew Alt 5 Deskew Sequence 1 Alternate word 5 UG001 Rev. 5.
Editors Chapter 3. Concepts BIST Settings Page These pages allow the customization of the BIST settings of the SerDes. Depending upon whether ”Enable lane-specific BIST Settings” is selected on the PCS Settings page, there will be either a single page configuring all lanes, or an individual page for each lane. Each page will have identical settings available to the user. Figure 3.62: BIST Settings Page – SerDes Configuration Editor 109 http://www.achronix.com UG001 Rev. 5.
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Editors Chapter 3. Concepts Advanced Page This page has no settings and is used to provide separation between the usual editor settings and the Register Settings page(s). Register Settings - Lane N Pages The Register Settings pages (there will be one for each enabled lane) allow the user to review and override any/all raw settings in the SerDes configuration registers. Figure 3.63: Register Settings - Lane 0 Page (Top Half) – SerDes Configuration Editor 111 http://www.achronix.com UG001 Rev. 5.
Editors Chapter 3. Concepts Figure 3.64: Register Settings - Lane 0 Page (Bottom Half) – SerDes Configuration Editor UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Editors Chapter 3. Concepts Register Settings Page Options Option Description AHB Address Filter Start Address Sets the starting address for filtering the registers displayed in ”AHB Register Settings”. Settings must be a hexadecimal value. End Address Sets the ending address for filtering the registers displayed in ”AHB Register Settings”. Settings must be a hexadecimal value. Function Filters the class of functions displayed in ”AHB Register Settings”.
Editors Chapter 3. Concepts VCD Waveform Editor The VCD Waveform Editor does not allow the user to edit a VCD file, it only allows viewing. But since it resides in the same location in the GUI as all the other Editors, and it opens whenever the user selects a VCD file, we’ll think of it as an editor in read-only mode. The waveform viewer allows the user to examine VCD output in a familiar waveform visualization, displaying how signals change values over time.
Editors Chapter 3. Concepts VCD Waveform Editor Options Description Option Signal Value Table Signal Name The name of the signal as stored in the VCD file. Value The value of the signal at the Marker’s indicated point in time. Waveform Timing Info Left The time (in ps) indicated by the left edge of the viewable waveform area. Right The time (in ps) indicated by the right edge of the viewable waveform area.
Editors Chapter 3. Concepts Zoom Out Decreases the zoom factor in the waveform area, decreasing the visible level of detail. Zoom to Marker Position Without changing the zoom factor, scrolls the waveform area horizontally to make the marker visible. Note: 2) Selected signals may also be moved up/down in the table with drag-and-drop using the mouse. There are also some icons used in the waveform signal value table. These are shown below. VCD Waveform Editor Icons Icon Description Signal Bus UG001 Rev.
Views Chapter 3. Concepts Views Views support Editors and provide alternative presentations as well as ways to navigate the information in the Workbench. For example, the Projects View displays projects and other resources currently being used. Views also have their own menus. To open the menu for a view, right-click the icon at the left end of the view’s title bar. Some views also have their own toolbars. The actions represented by buttons on view toolbars only affect the items within that view.
Views Chapter 3. Concepts Projects View The Projects view provides a hierarchical view of the projects in the Workbench. From here, projects can be added and removed, project configurations edited, the active implementation can be chosen, saved, or restored, files opened for editing, etc. Clicking on an implementation activates it. Similarly, clicking on a project activates the first implementation in the project definition. By default, the Projects view is included in the Projects perspective.
Views Chapter 3. Concepts Add source files Opens the Add Source Files dialog to allow the user to add source netlist and constraint files to the selected project in the Projects view. It also allows IP Configuration files (.acxip) to be added to the project as a convenience. Refresh contents Refreshes the listing of supporting files contained within the selected project or implementation. Remove Allows the user to remove the selected item from the Projects view.
Views Chapter 3. Concepts Flow View The Flow view provides a hierarchical view of flow steps that can be performed on the active implementation. From here, flow steps can be run and flow status viewed. Flow steps are not able to run unless an active implementation is selected in the Projects view. When running flow steps, the implementation options of the active implementation are used to govern the flow. By default, the Flow view is included in the Projects perspective.
Views Chapter 3. Concepts Flow category (running) Flow category (complete) Flow category (disabled) Flow category (error) Flow step (incomplete) Flow step (running) Flow step (complete) Flow step (disabled) Flow step (error) 121 http://www.achronix.com UG001 Rev. 5.
Views Chapter 3. Concepts Options View The Options view displays project implementation options for the active implementation. From this view, the active project implementation can be configured for its run through the flow. This view does not display any information unless an active implementation is selected in the Projects View. When Running the Flow, the implementation options of the active implementation are used to govern the flow.
Views Chapter 3. Concepts Speed Grade speed grade This option allows the user to select the desired speed grade for the target device. Core Voltage core voltage This option allows the user to select the core voltage for the target device. Junction Temperature junction temperature This option allows the user to select the junction temperature for the target device. Flow Mode flow mode Normal flow mode enforces all DRC checks as early in the flow as possible.
Views Chapter 3. Concepts Fanout Limit fanout limit Specifies the net fanout limit applied when fanout control is enabled for this implementation. Resynthesis Mode synthesis remap Specifies whether resynthesis should optimize for timing, area, or should be disabled. Optimizing for area can be used to reduce the total number of LUTs. When optimizing for timing, the optimizations performed will depend upon the strategies chosen below.
Views Chapter 3. Concepts Post-PnR Buffer Limit max postpnr buffer limit This limit specifies the maximum number of post-placement buffers that can be inserted. Post-PnR Rewiring postpnr rewire If turned on, allows post-pnr rewiring to better the design performance and resource usage. Placement Effort placement effort Low effort placement will have a shorter runtime, but may yield less design QoR than High effort placement.
Views Number of worst paths Chapter 3. Concepts sync timing num worst Maximum number of worst paths per end point. Bitstream Generation Implementation Options Option TCL Option Description Serial Flash (.flash) bitstream output flash This option enables the generation of an additional Serial Flash formatted output file. This file will be named the same as the STAPL file, but with a .flash extension. 4x Serial Flash (.
Views Chapter 3. Concepts Chain Offset of Target bitstream chain offset Specifies the offset of the target device on the JTAG scan chain for multi-device chains. Setting this to 0 selects the first device on the chain, 1 selects the second device on the chain, and so on. IR Bits Before Target bitstream preir padding Specifies the total number of Instruction Register bits on the JTAG scan chain prior to the target device Instruction Register.
Views Chapter 3. Concepts Resynthesis Strategy Details (within Advanced Design Preparation) ACE tries to improve QOR by resynthesizing portions of the design during the Run Prepare flow step. The Resynthesis Timing Rules (Rewrite Rule 1, Rewrite Rule 2, Move Flop-flop Reset, and Loop Speedup) only control the optimizations performed when Resyntheses Mode is set to Optimize for Timing (i.e. when the implementation option synthesis remap is set to timing).
Views Chapter 3. Concepts Multiprocess View The Multiprocess View ( tions Using Option Sets. ) allows Running Multiple Flows in Parallel and Attempting Likely Optimiza- The Multiprocess View provides a way for users to select multiple implementations within a single project for flow execution.
Views Chapter 3. Concepts (configured in Preferences) This link, when selected, will bring up the Multiprocess View Preference Page, allowing the user to configure the qsub command-line options which will be used when submitting jobs to the GridEngine. When the Parallel Job Count is set to the minimum value of 1, all selected implementations will be executed sequentially, one at a time.
Views Chapter 3. Concepts Existing Implementations This radio button will update the contents of the Implementation Table to show all existing implementations for the current active project. Generate Implementations from Option Sets This radio button will update the contents of the Implementation Table to show the current active implementation and a number of to-be-generated implementations, one per Option Set.
Views Chapter 3. Concepts Figure 3.71: Multiprocess View Screenshot Implementation Execution States There are a number of possible Execution States (as listed in the second column) for the implementations in the table corresponding to the lifetime of a Multiprocess View’s background process. The icons from these states are also used on the tabs within the Multiprocess Run Logs section. UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Views Chapter 3. Concepts Implementation Execution States and Icons Icon Execution State Description no icon blank This implementation has not been selected for execution. no icon Selected This implementation is currently selected for execution, and execution has not been started. In Queue Execution of the selected implementations has been started, this implementation was selected for execution, and this implementation is currently waiting in the queue for execution.
Views Chapter 3. Concepts Multiprocess Run Logs This section shows the logs for each selected implementation as they execute. A separate tab is provided for each individual implementation. The log info is updated live as the processes execute8 . (The displayed log info mirrors the information captured in the log file for each implementation.) Each tab will include the name of the implementation and the execution state, which updates live.
Views Chapter 3. Concepts Tcl Console View The Tcl Console view provides an interactive Tcl console for the tool. All user interactions that change design and project data go through the Tcl command interface, including all commands executed while in the GUI. From here, executed commands and their information is displayed, including any warning and error messages. This console can also be used interactively by typing Tcl commands directly into the console to manipulate projects or the current design.
Views Chapter 3. Concepts Search View The Search view provides an interface for searching the ACE design database for design objects (instances, nets, ports, pins, sites, and paths), displaying the results of a search in a list, organized by object type. Optionally, all or part of the results of a search can be added to the current selection, displayed in the Selection view. The Search View is a graphical interface to the Tcl command find.
Views Chapter 3. Concepts I/O Macro (Applies to ports) Instances (All instances will be under this branch of the search results.) Ports (All ports will be under this branch of the search results.) Pins (All pins will be under this branch of the search results.) Nets (All nets will be under this branch of the search results.) Paths (All paths will be under this branch of the search results.) Sites (All sites will be under this branch of the search results.
Views Chapter 3. Concepts Zoom To Y Zooms the Floorplanner view to a region containing the items currently chosen in the results list. Show in RTL Y If relevant data exists, opens a text editor to the file and line number relevant to the chosen result item. (Available only when a single item is chosen in the results list, and that item is an Instance or Net.) Note: this is Early Access functionality; this may not always open the text editor to the expected location.
Views Chapter 3. Concepts Search Results and ACE Selection The complete results of a search may be added to the current ACE selection set by checking the Add Results to Selection checkbox before starting the search. A subset of the search results may be added to the current ACE selection set by selecting the desired additions in the search ”Results” list and pressing the Add to Selection ( ) button. Or, a single entry in the ”Results” list can be double-clicked to add it to the current selection.
Views Chapter 3. Concepts Selection View The Selection view provides an interface allowing a user to view and manage the current selection set. A selection set consists of a collection of ACE design database objects. The selection set may also be manipulated with the Tcl commands select and deselect. The Selection view displays the current selection set in a list, organized by object type.
Views Icon 141 Chapter 3. Concepts Action Toolbar Button Context Menu Description Y Zooms the Floorplanner view to a region containing the current list of chosen objects in the Selection view. Zoom to selection Y Display next 200 objects Y Displays the next 200 objects in the selection set. Display Previous 200 objects Y Displays the previous 200 objects in the selection set.
Views Chapter 3. Concepts Show in RTL Y If relevant data exists, opens a text editor to the file and line number relevant to the chosen Selection item. (Available only when a single item is chosen in the Selection list, and that item is an Instance or Net.) Note: this is Early Access functionality; this may not always open the text editor to the expected location. For more information about the interaction between Selection and Highlighting, please see Search Highlights.
Views Chapter 3. Concepts Figure 3.74: Selection View 143 http://www.achronix.com UG001 Rev. 5.
Views Chapter 3. Concepts Critical Paths View The Critical Paths view provides a table of critical paths resulting from running timing analysis. This view displays critical path details, manages selection of objects on critical paths, and highlights critical paths in the Floorplanner view. The information shown in the view will differ slightly based upon whether the target device is synchronous (the 22iHD family) or asynchronous (the 22iHP family).
Views Chapter 3. Concepts domain. The clock domains themselves are (by default) sorted from most critical to least critical. Default sort order, from most critical to least critical, of the critical paths for Synchronous devices: 1. Setup violations, from the most negative slack value to zero 2. Hold violations, from the most negative slack value to zero 3. Setup met, from zero to the most positive slack 4.
Views Chapter 3. Concepts Run Post-Place Timing Analysis If selected, runs the Post-Place Timing Analysis flow step. Run Post-Route Timing Analysis If selected, runs the Post-Route Timing Analysis flow step. Run Final Timing Analysis If selected, runs the Final Timing Analysis flow step. Asynchronous Target Devices For asynchronous parts, the view will show a tree table, with each branch of the tree representing a separate clock domain.
Views Chapter 3. Concepts The View’s pull-down menu (to the right of the Toolbar buttons) contains some shortcuts to run the four stages of timing analysis. Critical Paths View Drop-down Menu Actions (Asynchronous) 147 Action Description Run Prepared Timing Analysis If selected, runs the Prepared Timing Analysis flow step. Run Post-Place Timing Analysis If selected, runs the Post-Place Timing Analysis flow step.
Views Chapter 3. Concepts Critical Path Diagram View The Critical Path Diagram view will provide a graphical representation of a single critical path. Selecting a row in the Critical Paths view’s table will cause the Critical Path Diagram view’s diagram to update so that it contains a graphical representation of the selected critical path. The graphical representations will consist of circular nodes (representing instances) connected by arrows (representing one or more nets).
Views Chapter 3. Concepts Critical Path Diagram View Toolbar Buttons Icon Action Description Selection tool Controls the behavior of the mouse while in the Critical Path Diagram view. The selection tool creates a selection rectangle when the left mouse button is pressed and held. Any objects in the selection rectangle are applied with the current selection action, as configured in the fly-out palette. Movement tool Controls the behavior of the mouse while in the Critical Path Diagram view.
Views Chapter 3. Concepts Arrows connecting nodes for a reconvergent path diagram will point in the direction of the asynchronous data flow, which (due to the underlying async ’ack’ backward-propagation) is sometimes in the opposite direction of the User Logic. These backward-propagation signals will be shown with dotted line arrows.
Views Chapter 3. Concepts Delays Displays the delay (in ps) to traverse each node or arrow. Fanouts Displays the fanout of the net represented by the arrow.4) Instance Names Displays the instance name each graph node represents. Instance Types Displays the instance type (cell) for each graph node. Net Names Displays the net name represented by each arrow.4) Note: 3) Only relevant for asynchronous devices. Synchronous target devices will not report stages.
Views Chapter 3. Concepts Package View The Package view provides a graphical view of the package layout of the device. This view allows the user to visualize the device package, and place device I/Os. Clicking on the tall narrow arrow on the far right of the Package view shows or hides the fly-out palette of display options for the Package View. By default, the Package view is included in the Floorplanner perspective. perspective, select Window → Show View → Package. To add it to the current Figure 3.
Views Chapter 3. Concepts Selection tool Controls the behavior of the mouse while in the Package view. The selection tool creates a selection rectangle when the left mouse button is pressed and held. Any objects in the selection rectangle are applied with the current selection action, as configured in the fly-out palette. Placement tool Controls the behavior of the mouse while in the Package view.
Views Chapter 3. Concepts Select Enabled This radio button controls the action applied to objects in the selection region. This setting causes the objects to be added to the current ACE selection set. Deselect Disabled This radio button controls the action applied to objects in the selection region. This setting causes the objects to be removed from the current ACE selection set. Remove Placement Disabled This radio button controls the action applied to enabled objects in the selection region.
Views Chapter 3. Concepts Design Port Names Labels The Enabled Displays the RTL port names of placed instances under the current mouse position in the tooltip text. Label options control the text labels on objects in the Package view. Label Options Option Default Description None Disabled Disables the display of label text in the package graphic.
Views Chapter 3. Concepts IO Assignment View The IO Assignment view provides a tabular representation of the properties of the I/O instances used in the current design. The view will remain empty until the currently active Implementation has been prepared (had the Run Prepare flow step completed). By default, the IO Assignment view is included in the Floorplanner perspective. To add the view to the current perspective, select Window → Show View → Other. . . → IO Assignment. See also: Managing I/Os.
Views Chapter 3. Concepts not match the current filter value. All displayed rows will, in the selected column, contain text that matches the applied filter. The portion of the text that matches the filter will be highlighted (in green). By default, the column being filtered is the Port Name column. To select an alternate column for the filter, first select the Selected Column radio button, then leftclick the corresponding column header. The selected column will be indicated in a platform-specific manner.
Views Chapter 3. Concepts Save Changed Properties Opens the ”Save Changed Properties Dialog”. Allows the user to save an .sdc file containing all properties changed (for all instances, not just I/Os) since the last time the Run Prepare flow step was executed. For more information, see Managing I/Os. Generate Pin Assignment Report Opens the ”Generate a Pin Assignment Report Dialog”. Allows the user to generate a Pin Assignment Report with the same column configuration as the current IO Assignment table.
Views Chapter 3. Concepts Voltage Level The VDD voltage level for this IO, set via the IO Standard selection. VREF Level The VREF voltage level for this IO, set via the IO Standard selection. Pad Polarity The LVDS polarity of this IO instance in the user design. This only applies for differential IO buffers and is set in synthesis. Pad DQ Capability The DQ capability of this IO instance in the user design. This only applies for byte lane IOs.
Views Chapter 3. Concepts Clock Regions View The Clock Regions view provides a tabular representation of the site type content of each clock region in the currently selected Target Device, and allows the user to toggle the visibility of the overlay within the Floorplanner view for each Clock Region. The view’s table will remain empty until the currently active Implementation has been prepared (had the Run Prepare flow step completed).
Views Chapter 3.
Views Chapter 3. Concepts Netlist Browser View The Netlist Browser view’s purpose is to provide a graphical, tree-based visualization of the user’s design hierarchy, as found in the netlist. The displayed netlist includes the results of any transformation, legalization, etc. that have happened through the current stage in the Flow. For large designs, there are a tremendous number of objects in the netlist.
Views Chapter 3. Concepts A number of actions are available in the view, via buttons at the top of the view, and (right-click) context menus on the nodes of the tree. Note that if these actions are performed upon macros or clock domains, all child leaf nodes, even those currently filtered to be hidden in the tree, will be affected by the chosen action.
Views Chapter 3. Concepts Group By Clock Domain When enabled, all instances in the netlist will be grouped in the tree under their relevant clock domain(s). (The clock domains become the root nodes of the tree.) When disabled, clock domain information is not displayed in the tree. Show Core Instances Toggles the display of leaf instances which are in the core of the target device. Show IO Ring Instances Toggles the display of leaf instances which are in the IO Ring of the target device.
Views Chapter 3. Concepts Placement Regions View The Placement Regions view provides a tabular representation of the content of all user-created Placement Regions for the design. The view allows the user to manipulate the visibility of the Placement Region, and manipulate the content (the instances constrained to the region) of each Placement Region. The view’s table will remain empty until the currently active Implementation has been prepared (had the Run Prepare flow step completed).
Views Chapter 3. Concepts Highlight Instances Highlights all instances constrained to the currently selected placement region with the currently-selected highlight color. The highlighted results will be visible in the Floorplanner view. Un-Highlight Instances Turns off the highlight color in the Floorplanner view for all instances constrained to the selected Placement Region. Zoom to Zooms the Floorplanner view to show the selected Placement Region.
Views Chapter 3. Concepts appear near the right-hand edge of that table cell. By selecting the ”. . . ” button, the user will be able to use the Color Dialog to choose the desired color for the placement region.
Views Chapter 3. Concepts Outline View The Outline view provides an alternate method for navigating the IP Configuration Editors. Selecting an item in the Outline view selects the associated page of the editor. The display is dynamic the contents of the outline will be updated as configuration settings are altered in the editor pages. Figure 3.84: Outline View Outline View Icons Icon Description Active page; no errors or warnings Warning on page. Error on page.
Views Chapter 3. Concepts IP Libraries View The IP Libraries view provides an alternate method for creating IP configuration files (.acxip) versus the main menu (File → New → IP Configuration. . . ). Expanding a device family name displays a list of available IP types for that family, double-clicking the IP type or clicking the Create New IP Configuration button opens the New IP Configuration dialog. Figure 3.
Views Chapter 3. Concepts IP Diagram View The IP Diagram view is meant to provide a graphical visualization of the configuration of the IP currently being edited. As different IP configurations are selected (by selecting their Editor), the IP Diagram view contents will change to reflect the selected IPs configuration.
Views Chapter 3. Concepts Figure 3.88: Example IP Diagram for PLL Editor with some errors in red The user may left-click on any text label in the IP Diagram to immediately turn the IP Editor to the associated page so that the user may edit the related Configuration Options. There are a number of preferences available allowing visual customization (colors and fonts) of the IP Diagram view - these are changed on the IP Diagram Preference Page. See also: Creating an IP Configuration 171 http://www.
Views Chapter 3. Concepts IP Problems View The IP Problems view displays a table of any warnings and errors found in the IP configurations for the currently open IP Configuration Editors. This view also displays detailed information on the error or warning plus a method for navigating to the error or warning. Clicking on an error or warning displays detailed information in the information pane below the navigation pane.
Views Chapter 3. Concepts IP Problems View Table Columns Column Name Description Summary A brief summary statement of the IP Configuration problem. File The IP Configuration file (.acxip) containing the error. This is the name of the file being edited in an open IP Configuration Editor. Property The property which is part of the IP Configuration problem. (Individual properties usually are similar to the field names shown in the IP Configuration Editor.
Views Chapter 3. Concepts Download View The Download view provides a graphical interface for playing a STAPL11 file to an Achronix FPGA connected via a Bitporter pod. By default, the Download view is included in the Bitporter Perspective. To access the Download view, select Window → Show View → Others → Download View. When the Download view opens, the windows may need to be resized for optimal viewing.
Views Chapter 3. Concepts Download View Options Option Description STAPL design file Default File from Current Design/Impl The STAPL design file will correspond to the bitstream file of the currently active implementation (design name.jam). Manual Selection and Browse Allow the user to choose/enter any STAPL design file from the file system. The textfield showing the filename is also a drop-down combobox of the last 15 *.jam files selected.
Dialogs Chapter 3. Concepts Dialogs Create Project Dialog The Create Project dialog helps users create a new project in the Workbench. After indicating a name and location for the project, click Finish to create the project. Figure 3.91: Create Project Dialog Create Project Dialog Fields Field Description Default Project Directory The location in the file system where the project is created. Users can either type the new location or browse to select a file system location for the new project.
Dialogs Chapter 3. Concepts Load Project Dialog The Load Project dialog is used to browse to find an existing project file to load into the Workbench. After selecting the project file and choosing to activate an implementation, click Finish to load the project. Figure 3.92: Load Project Dialog Load Project Dialog Fields Field Description Project File The file path to the ACE Project File (.acxprj) to load.
Dialogs Chapter 3. Concepts Create Implementation Dialog The Create Implementation dialog is used to create a new implementation in the selected project. After indicating a new name for the implementation and whether to copy option values from the active implementation, click Finish to create the implementation in the selected project. Figure 3.
Dialogs Chapter 3. Concepts Restore Implementation Dialog The Restore Implementation dialog is used to retore the database state of the active implementation from an Acxdb Archive File. After indicating the file path to the Acxdb Archive File to restore the implementation from, click Finish to restore the active implementation. Figure 3.
Dialogs Chapter 3. Concepts Save Implementation Dialog The Save Implementation dialog is used to save the database state of the active implementation to an Acxdb Archive File. After indicating the file path to the Acxdb Archive File to save the implementation to and whether to include the log file, click Finish to save the active implementation. Note: Implementations may only be saved after the Run Prepare flow step has been completed. Prior to that, there is no meaningful content in the database to save.
Dialogs Chapter 3. Concepts Create a New Constraints File Dialog The Create a New Constraints File Dialog is used to easily create a new, empty constraints file and optionally add it to the currently active project. The dialog is available in all perspectives, and can be accessed by selecting File→New→SDC Constraints File. . . . Figure 3.96: Create a New Constraints File Dialog Screenshot The dialog allows the user to type the file’s destination Directory, or select it graphically using the Browse. . .
Dialogs Chapter 3. Concepts Create a New Text File Dialog The Create a New Text File Dialog simply allows the user to create a new text file and open it in the ACE text editor in a single action. The dialog is available in all Perspectives, and can be selected via File → New → Text File. . . . Figure 3.97: Create a New Text File Dialog Screenshot The dialog allows the user to type the file’s destination Directory, or select it graphically using the Browse. . . button.
Dialogs Chapter 3. Concepts Add Source Files Dialog The Add Source Files dialog is used to browse for netlist (.v and .vma), constraints (.sdc and .pdc), and IP Configuration (.acxip) source files to add to the selected project. After selecting the files to add, click Open (in Windows) or OK (in Linux) to add them to the project. Figure 3.98: Add Source Files Dialog When files with unrecognized file extensions are added to a project (possible when the ”*.
Dialogs Chapter 3. Concepts Figure 3.99: Add Source Files Categorization Dialog The categorization dialog will contain the list of unknown files on the left, with the allowed categories for each file on the right. Files may be moved into and out of the categories with the and buttons, respectively. Once all the files are categorized, press the Finish button to add the files to the active ACE project, or press Cancel to add none of the files. UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Dialogs Chapter 3. Concepts Save Placement Dialog The Save Placement dialog saves the current placement to pre-placement constraints file(s). After selecting the appropriate options, click Finish to save the placement. Figure 3.100: Save Placement Dialog Save Placement Dialog Fields Field Default Description Save I/O Placement Enabled This option indicates whether placement of instances in the I/O ring should be saved. I/O Placement File 185 http://www.achronix.com UG001 Rev. 5.
Dialogs Use Default Location Chapter 3. Concepts Enabled Selects whether the default I/O placement file path is used, or the one manually specified below the option. Enabled This option indicates whether placement of instances in the core fabric should be saved. Enabled Selects whether the default core placement file path is used, or the one specified below the option.
Dialogs Chapter 3. Concepts Save Script File Dialog The Save Script File dialog is used to create a Tcl script of find commands for the current list of critical paths for use in the schematic viewer of the synthesis tool. After indicating a filename and location for the Tcl script, click Save to write the script to disk. Figure 3.101: Save Script File Dialog 187 http://www.achronix.com UG001 Rev. 5.
Dialogs Chapter 3. Concepts New IP Configuration Dialog The New IP Configuration dialog helps users create a new IP configuration file (.acxip). After indicating a name and location for the configuration file, click Finish to create the file and open the relevant IP Configuration Editor. See also: Creating a New IP Configuration. Figure 3.102: New IP Configuration Dialog New IP Configuration Dialog Fields Field Description Available IP Lists the available IP blocks by FPGA family.
Dialogs Chapter 3. Concepts Generate IP Design Files Dialog The Generate IP Design Files dialog is used to create the necessary RTL models, timing constraints and bitstream files for configuring embedded IP. The files generated are based upon the configuration file (.acxip) created via the active IP Configuration Editor. See also: Creating an IP Configuration. Figure 3.
Dialogs Chapter 3. Concepts Placement Constraints Selected Selects whether a placement constraints file for the configuration is generated.(1) Additional Generate IP Design Files Dialog Fields (SerDes-only) Field Default Description Bitstream Configuration Quad 0 Bitstream Config Selected Selects whether a bitstream file for Quad 0 for the configuration is generated.(1)(3) Quad 1 Bitstream Config Selected Selects whether a bitstream file for Quad 1 for the configuration is generated.
Dialogs Chapter 3. Concepts Configure Selected IOs Dialog The ”Configure Selected IOs Dialog” allows the user to configure the electrical settings for the currentlyselected I/Os in the ”IO Assignment View”. Changes made from this dialog will not require that PnR be re-run. See Managing I/Os for more info. Figure 3.104: Configure Selected IOs Dialog There are a number of fields that may be edited from the dialog - these are shown in the table below.
Dialogs Chapter 3. Concepts Change On Die Termination to Enabling this option allows the user to change the On Die Termination setting of the selected IOs to a new value. This property does not apply for Outputs. Change Termination Value to Enabling this option allows the user to change the Termination value of the selected IOs to a new value. This property does not apply for Outputs and only applies if On Die Termination is turned on.
Dialogs Chapter 3. Concepts Save Changed Properties Dialog The ”Save Changed Properties Dialog” allows the user to save to an .sdc file any properties that have been changed since the Run Prepare flow step was last executed. Figure 3.105: Save Changed Properties Dialog To perform this action without using the dialog, use the Tcl command save properties. See also: IO Assignment View and Managing I/Os. 193 http://www.achronix.com UG001 Rev. 5.
Dialogs Chapter 3. Concepts Generate a Pin Assignment Report Dialog The ”Generate a Pin Assignment Report” dialog allows the user to generate a customized Pin Assignment Report with a column organization identical to the current organization of the columns in the ”IO Assignment View”. Figure 3.106: Generate a Pin Assignment Report Dialog UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Dialogs Chapter 3. Concepts Configure Table Columns Dialog The ”Configure Table Columns Dialog” allows the user to configure the columns shown in the active view. Currently this dialog is only available for the IO Assignment View. From the dialog, the user may configure which columns are visible and the width (in pixels) of each column. The user may also save the current column configuration to a file, or load a previous column configuration from a file. Figure 3.
Dialogs Chapter 3. Concepts Add Signals to Waveform Viewer Dialog This dialog allows the user to add signals to the table and waveform area of the VCD Waveform Editor. The dialog allows the user to either unhide signals which were previously hidden via the Remove button in the VCD Waveform editor, or add duplicates of already-shown signals to the table and waveform. The selected signals may added at either the top or bottom of the table/waveform via the dialog.
Dialogs Chapter 3. Concepts 1) This button may be pressed multiple times for a given signal, which will add the signal selected in the dialog’s list to the VCD Waveform Editor’s signal table multiple times. This button will be disabled if no signal is currently selected in the dialog’s signal list. If this button is used to un-hide a previously-hidden signal, the signal will be removed from the list of hidden signals (because it is no longer considered hidden).
Dialogs Chapter 3. Concepts Assign Bussed Signal Names Dialog The Assign Bussed Signal Names Dialog wizard allows the user to combine multiple signals from the SnapShot Debugger view’s ”Monitor Channels” table into a bus. After configuring the bus in the dialog, the bus name and indices are propagated to all the selected signals, changing the signal names appropriately. The bus/signal names will then be used in the SnapShot sampled output, visible in the VCD Waveform Editor.
Dialogs Chapter 3. Concepts Search Filter Builder Dialog This wizard dialog allows the user to build simple or compound search filters to be used in the Search View. Search filters are used to find objects in the design based upon properties other than object name. Simple filters may be combined into a compound filter by joining them with Boolean operators. Figure 3.110: Search Filter Builder Dialog screenshot Search Filter Builder Dialog Option Description Filter The filter string itself.
Dialogs Chapter 3. Concepts EQUAL Select this radio button when you want to join two filters into a compound filter where the Boolean value of both sub-filters is identical. Insert Operator Press this button to insert the selected Boolean operator into the Filter field at the current text cursor position within that field. Filters Name This is a combo box showing all the choices of supported filter parameter names.
Dialogs Chapter 3. Concepts Create Placement Region Dialog This wizard dialog appears after the user has used drag-and-drop to define a rectangular area in the Floorplanner view while the Placement Region Tool is active. It allows the user to name the new Placement Region, and define its bounds. See also: Creating a New Placement Region. Remember Placement Regions are only supported for the 22iHD family of Achronix devices. Figure 3.
Dialogs Snap to Tile Boundaries Chapter 3. Concepts If selected, ACE will create a Placement Region that encompasses all Tiles selected within the drag-and-drop rectangle. Note that since Placement Regions can only contain entire sites (no partial sites), the Placement Region will potentially grow larger than the outline rectangle. Subtile Grid Coordinates16 X1 Coordinate The upper-left X coordinate within the subtile grid, corresponds to the left edge.
Dialogs Chapter 3. Concepts Save Placement Regions Dialog This wizard dialog appears after the user has selected the ”Save Placement Regions” action in the Placement Regions view. It allows the user to save placement region definitions, including the instance constraints for those placement regions. See also: Saving Placement Region Constraints. Figure 3.
Toolbars Chapter 3. Concepts Toolbars There are three kinds of toolbars in the Workbench: main, view, and fast view. The main toolbar, sometimes called the Workbench toolbar, is displayed at the top of the Workbench window directly beneath the menu bar. The contents of this toolbar change based on the active perspective. Items in the toolbar might be enabled or disabled based on the state of either the active view or editor. Sections of the main toolbar can be rearranged using the mouse.
Preferences Chapter 3. Concepts Preferences The ”Preferences dialog” is used to set user preferences. The Preferences dialog pages can be searched using the filter function. To filter by matching the page title, simply type the name of the page being sought, and the available pages are presented below. The filter also searches on keywords such as ”appearance” and ”text”. The history controls allow navigation through previously viewed pages.
Preferences Chapter 3. Concepts Critical Path Diagram View Preference Page This page configures the display preferences of the Critical Path Diagram view. Figure 3.114: Critical Path Diagram View Preference Page Critical Path Diagram View Preference Page Options Option Description Labels Configures the color of the label text printed for graph nodes and arrows in the diagram. Outline Configures the color of the outline of the graph nodes in the diagram.
Preferences Cancel 207 Chapter 3. Concepts When this button is pressed, any preference configuration changes made since the dialog was opened (or since the last time an Apply button was pressed in the dialog, whichever was most recent) are discarded. http://www.achronix.com UG001 Rev. 5.
Preferences Chapter 3. Concepts Floorplanner View Colors Preference Page The Floorplanner View Colors Preference Page configures multiple layer color preferences for the Floorplanner view. Figure 3.115: Floorplanner View Colors Preference Page UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Preferences Chapter 3. Concepts Floorplanner View Optimizations Preference Page The Floorplanner View Optimizations Preference Page configures rendering optimizations for the Floorplanner view. Figure 3.116: Floorplanner View Optimizations Preference Page There are numerous rendering optimizations available to the Floorplanner, and ACE allows different configurations for three levels of design complexity. The cutoffs between complexity levels may also be configured.
Preferences Chapter 3. Concepts Optimization settings which may vary with design complexity Option Technical Description When panning, show only background layer: The amount of rendering performed while panning is reduced, and the detailed render only occurs after panning/scrolling is completed.
Preferences Chapter 3. Concepts Max unsegmented area: Reduce overdraw with route preprocessing and caching: Max zoom level to be preprocessed/cached: Areas larger than this will be broken into smaller chunks up to Max re-quartering recursion times. Relevant at the outermost zoom levels. Decreasing this will increase total render times, but can provide more frequent visual feedback. Improves render speeds by reducing route line overdraw via culling.
Preferences Technical Note for Windows Users Chapter 3. Concepts The Windows operating system requires that applications check-in every five seconds, or the application is deemed non-responsive. Non-responsive applications are given a figurative kick-in-the-pants, and asked to repaint the screen. When the screen paint itself is taking more than five seconds, an application can be forced into an effective infinite-loop of paint requests from the operating system.
Preferences Chapter 3. Concepts IP Diagram Preference Page There are a number of preferences for the ”IP Diagram View” relating to colors and fonts. Figure 3.117: IP Diagram Preferences IP Diagram Preferences Options Option Description Block Diagram Font This will be the font used to title logic blocks in the diagram. Default Font This font will be used for all diagram text except the logic block titles. Normal Foreground Color This color will be used for logic blocks, signals, and text.
Preferences Error Background Color Chapter 3. Concepts Text representing IP Options with errors will have their backgrounds painted this color. UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Preferences Chapter 3. Concepts Multiprocess View Preference Page This page allows the user to manage custom command-line options for the qsub command used by the Multiprocess View. The qsub command is called when submitting implementation execution processes to an external GridEngine (like OGE)17 . Figure 3.
Preferences Caution: 19 meaning Chapter 3. Concepts Debugging qsub configurations: If the GridEngine and qsub are properly configured19 on the host machine, and ACE is still unable to successfully submit jobs to the GridEngine, please contact Achronix technical support. While ACE does provide the complete attempted qsub command in the Multiprocess Run Logs section of the Multiprocess view, DO NOT copy the text of the attempted command and manually attempt the same command from the command-line.
Preferences Chapter 3. Concepts Other Colors and Fonts Preference Page Many of the fonts and colors and used by ACE components can be set using the General → Appearance → Other Colors and Fonts to open the ”Other Colors and Fonts” preference page. A tree is used to navigate among and show a short preview of the various colors and fonts. The current face (but not size) of any font is previewed in its label. Colors are previewed in the icon associated with its label.
Preferences Chapter 3. Concepts Package View Preference Page View settings for the Package view are set via the Package View preference page. This page currently provides color configuration for several graphics layers in the Package view. Figure 3.120: Package View Preference Page UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Preferences Chapter 3. Concepts Placement Regions Preference Page The Placement Regions Preference Page configures how Placement Regions are handled in the Placement Regions view and the Floorplanner view (when the Floorplanner’s Placement Region Tool is active). NOTE: Placement Regions are only presently supported for the 22iHD family of parts. Figure 3.
Preferences Chapter 3. Concepts Project Management Preference Page The behavior of editors and reports is set from the Project Management Preference Page. Figure 3.122: Project Management Preference Page UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Preferences Chapter 3. Concepts Tcl Console View Preference Page The Tcl Console View Preference Page contains settings that alter the behavior and/or presentation of information in the Tcl Console view. Figure 3.123: Tcl Console Preference Page Tcl Console View Preferences Option Description Tcl Console Font Allows the user to chose the font used in the Tcl Console.
Preferences Chapter 3. Concepts Text Editors Preference Page The behavior and appearance of the text editor can be set from the Text Editors Preference Page. Figure 3.124: Text Editors Preference Page Text Editor Options Option Default UG001 Rev. 5.0 - 5th December 2012 Description http://www.achronix.
Preferences Chapter 3. Concepts Undo history size 200 Sets the undo history size. Display tab width 4 Sets the tab width for the editor. Insert spaces for tabs Deselected Enables insertion of spaces for tab characters. Highlighting current line Selected Enables/disables the highlighting of the current line. The highlight color is set in ”Appearance color options.” Show print margin Deselected Enables the visibility of the print margin.
Preferences Chapter 3. Concepts Quick Diff Preference Page The Quick Diff preferences can be changed on the Quick Diff preference page, accessed via Text Editors → Quick Diff. Figure 3.125: Quick Diff Preference Page Quick Diff Preference Page Option Default Description Enable quick diff Selected Enables/disables the quick diff option. Show differences in overview ruler Deselected This option shows differences in the overview ruler. Colors Changes Sets the color indicating changes.
Projects Chapter 3. Concepts Projects A project represents the collection of source netlist and constraints files, flow options, IP configuration files, and output files for a particular design. Implementations A Project may have multiple implementations. Each implementation contains the set of flow options (also called implementation options) configuring the project’s run through the flow, and the flow outputs for this particular configuration.
Projects Chapter 3. Concepts Option Sets only enable performance-related implementation options, and (currently) never disable any already-enabled implementation options. So each generated implementation starts with the exact same implementation options as the template implementation, and then just the few implementation options named in the Option Set’s description are overwritten with the described values. Achronix broke up the Option Sets into small granular chunks because of QOR/runtime tradeoffs.
Projects Chapter 3. Concepts Project File Projects are persisted in project files (.acxprj file extension) created automatically by the tool whenever a project is saved. A project file is actually just a Tcl script supporting only a defined subset of Tcl commands. Users can edit project files manually and then load them into the tool to use as a script or for running regressions. In the GUI, loaded project file contents are displayed in a tree structure in the Projects view.
Projects Chapter 3. Concepts associated with a project. When associated with a project, these IP Configuration files may then be browsed in the Projects view under the projects IP folder, and the associated editor may be started by double clicking on the file name in the Projects view. For more details, see Creating an IP Configuration, SerDes Configuration Editor, FIFO Configuration Editor, I/O Configuration Editor, and PLL Configuration Editor.
Projects Chapter 3. Concepts Multiprocess Log Unlike normal flow executions, implementation runs initiated from the Multiprocess View do not have their log information appended to the ACE Session Log. This is because multiple processes would be appending info to the log file simultaneously, which would leave log entries interleaved in an unreadable mess. Instead, each implementation executed in the background will create a new log file named multiprocess.log in that implementation’s log directory.
Flow Chapter 3. Concepts Flow The flow is the set of steps that must be run to complete a design in ACE. A flow can only be run on an active project implementation, and only on one project’s implementation at a time during an interactive ACE session. To run multiple implementations from the same project through the flow simultaneously, use the Multiprocess View. To run multiple implementations from separate projects through the flow simultaneously, multiple sessions of ACE must be run.
Reports Chapter 3. Concepts Reports ACE generates a number of reports to inform users how their designs are being handled in the selected Achronix device. These reports are meant to assist the user when making design decisions.
Reports Chapter 3. Concepts Timing Report The Timing Report provides details on how well the current design is meeting timing on the selected device. Timing analysis can be performed at several stages in the flow, each stage generating a different report. If the design has not yet been routed, placement and/or routing are estimated. The Timing Reports will, of course, contain different details based upon whether the chosen target device is synchronous or asynchronous.
Reports Chapter 3. Concepts each clock is analyzed in isolation, ignoring the relations between them. (For clocks which have no related clocks, the result is the same as for part II.) By necessity, the analysis in part III must make an approximation at the boundaries between clock domains, and should not be interpreted as describing the actual behavior of the circuit. For this reason, part III is disabled by default.
Reports Chapter 3. Concepts Timing Results Summary Section The Timing Results Summary section of the report will only be generated if either the ”Run Post-Route Timing Analysis” or ”Run Sign-off Timing Analysis” flow steps are enabled in the Flow view when Multiprocess execution is started. Achieved Frequency cells are color-coded to indicate whether the Target Frequency was achieved for each implementation’s defined clock domains.
Advanced Concepts Chapter 3. Concepts Advanced Concepts The following are advanced concepts intended primarily for extremely experienced users, or users being actively guided by Achronix FAEs. Clock Regions Synchronous fabrics (like those found in the 22iHD family) deal with numerous clocks. Due to physical routing limitations, only a finite number of clocks can be routed to each individual site within the fabric.
Chapter 4. Tasks Tasks Running ACE ACE can be run in three different modes: • GUI • Command line • Batch To run in GUI mode, invoke the ace executable either with no options or with the -gui option. GUI mode launches the interactive GUI, from which all commands are issued. To run in command-line mode, invoke the ace executable with the -b option from a console. Commandline mode takes control of the console and allows the user to interactively enter Tcl commands at a command prompt.
Working With Perspectives Chapter 4. Tasks Working With Perspectives Perspectives define the initial set and layout of views in the Workbench window, providing a set of functionality aimed at accomplishing a specific type of task or working with specific types of resources. Switching Between Perspectives Each perspective has an associated icon on the main toolbar. Switch between perspectives by clicking the icons on the main toolbar.
Working with Views and Editors Chapter 4. Tasks Working with Views and Editors Views and editors are the main visual entities appearing in the Workbench. In any given perspective there is a single editor area, which can contain multiple editors, and a number of surrounding views providing context. Opening Views Perspectives offer pre-defined combinations of views and editors. To open a view not included in the current perspective, select Window → Show View from the main menu bar.
Working with Views and Editors Chapter 4. Tasks Creating Fast Views Fast views are hidden views that can be quickly opened and closed. These views work similar to other views except they do not take up space in the Workbench window. To create a fast view: 1. Click and hold on the title bar of the view to be saved as a fast view. 2. Drag the view to the Fast View bar and release the mouse button. By default the shortcut bar is located in the lower left corner of the window.
Working with Projects and Implementations Chapter 4. Tasks Working with Projects and Implementations Creating Projects To create a new project in the workspace: 1. Click on the Create Project toolbar button ( ) in the Projects view. 2. In the Create Project dialog, type in or browse to the location of the new project directory. Note: Directories in the path that do not exist are created. 3. Type in the new project name and click Finish.
Working with Projects and Implementations Chapter 4. Tasks Figure 4.1: Unsaved Project View 2. Either press CTRL+S on the keyboard, select the File → Save ( or select the File → Save menu option. ) toolbar button on the main toolbar, To save a project to a different file: 1. Select the project in the Projects view. 2. Select the File → Save As. . . menu option. 3. Browse to a new file location 4. Enter a project name and click Save.
Working with Projects and Implementations Chapter 4. Tasks Figure 4.2: Unsaved Changes Prompt Opening Project Files in an Editor To open a project file in the editor area, double-click on the project in the Projects view. The project file now appears in a text editor in the editor area. Editing a project file in the workspace does not affect the project unless the project is removed and then re-loaded from the changed project file.
Working with Projects and Implementations Chapter 4. Tasks 4. Select one or more files, and click Open. After clicking Open, the source files appear in the appropriate netlist or constraints folder under the selected project in the Projects view. The source files are not actually loaded into the design until run prepare is called. Adding a source file to a project simply creates a link to the file so that it may be loaded during run prepare.
Working with Projects and Implementations Chapter 4. Tasks Saving Implementations To save the state of the database (options, netlist, constraints, placement, and routing data) for an implementation in a project in the workspace: 1. Activate an implementation in the Projects View. 2. Run the flow (at least through Run Prepare) 3. Optionally edit placement or routing information 4. Click on the Save Implementation toolbar button ( ) in the Projects view. 5.
Working with Projects and Implementations Chapter 4. Tasks Copying Implementations To create a new implementation that is a copy of an existing implementation, 1. In the Projects View, select (activate) the implementation to be copied 2. Select the Create Implementation ( ) toolbar button in the Projects View 3.
Working with Projects and Implementations Chapter 4. Tasks Opening Report Files in an Editor To open a report file in the editor area, double-click on the report file in the Projects view. The report file now appears in a web browser in the editor area. Note: Editing a report file is not recommended. UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Running the Flow Chapter 4. Tasks Running the Flow A flow can only be run on the current active implementation. If no active implementation is set in the Projects view, then the flow steps in the Flow view are disabled. Some flow steps are optional while others are required. Optional flow steps may be enabled or disabled in the flow by checking or un-checking the checkbox to the left of each flow step label. Running the Entire Flow To sequentially run through all of the available flow steps in order: 1.
Running the Flow Chapter 4. Tasks Run Estimated Timing Analysis (Optional) After Run Prepare has successfully completed on an implementation, the Run Estimated Timing Analysis step can be run. This step generates and writes a pre-place-and-route timing report file for the prepared design. The generated report is automatically displayed in the editor area upon successful completion. This step is run by default when Run Flow is executed.
Running the Flow Chapter 4. Tasks final simulation netlist can be generated without errors. If your design fails final DRC checks, you can still generate a Post-Route timing report for experimental purposes. However, no bitstream may be generated to run the design on the hardware unless all final DRC checks pass. Run Sign-off Timing Analysis (Optional) After Run Final DRC Checks has successfully completed on an implementation, the Run Sign-Off Timing Analysis step can be run.
Running the Flow Chapter 4. Tasks Configuring the Execution Queues Within the Multiprocess view, the ”Execution Queue Management” section allows the user to configure the desired number of parallel processes used to consume the queue of selected implementations. Simply set the value of Parallel Job Count to the desired number of parallel processes. Using the minimum value of 1 will cause all queued implementations to be executed sequentially, one after another.
Running the Flow Chapter 4. Tasks A = R - ( O + G + B + U ), where R = total RAM installed in the workstation O = amount of memory required by the Operating System G = amount of memory required by the currently-running ACE GUI B = amount of memory required by the currently-running ACE backend process (named acx or acx.
Running the Flow Chapter 4. Tasks and ACE is still unable to successfully submit jobs to the GridEngine, please contact Achronix technical support. WARNING: Attempting to manually run the logged qsub command (without the Multiprocess View’s additional automated safety locks in place) may cause ACE datafile corruption.
Running the Flow Tip: Chapter 4. Tasks If the implementation table isn’t large enough (or is too large) for the full implementation list, simply collapse and/or expand one of the other sections in this view. (Left-click the section title.) This will cause the table to resize to exactly fit the current implementation list.
Running the Flow Chapter 4. Tasks of the captured error messages. Error details will be visible in the log messages shown in the tab, as well as within the Implementation Log and Multiprocess Log for that implementation. UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Using the Tcl Console Chapter 4. Tasks Using the Tcl Console Any operation that changes project or design data can be performed from the command line via a Tcl command. The Tcl Console view provides an interface from within the GUI for viewing and executing Tcl commands. Sending Commands from GUI Actions Any action in the GUI that changes project or design data automatically sends a Tcl command through the Tcl Console view to do the work.
Using the Tcl Console Chapter 4. Tasks ENTER on a selected command to complete it at the command prompt. Typing while the command autocompletion dialog is open shortens or lengthens the list of valid commands, depending on the cursor position in the TCL Console view. Figure 4.4: TCL Command Auto-completion Command Help When the command auto-completion dialog is open, help text appears to the right of the command list for the selected command.
Using the Tcl Console Chapter 4. Tasks Figure 4.5: Help Text Display Figure 4.6: Help Text Displayed in TCL Console Text Limit The TCL Console view has a limit of 2000 lines. Once this limit is reached, any new lines entered via commands or message text causes the text at the top of the TCL Console to be pruned. Additionally, when Tcl command return values are displayed in the Tcl Console, any long returned values will be visually truncated at 500 characters in the console.
Using the Tcl Console Chapter 4. Tasks Viewing the ACE Log File All TCL commands and messages issued during an ACE session are recorded in the ACE log file. If the text limit is reach from excessive messages, it is sometimes useful to browse the log file for previous messages. To open the ACE log file in the editor area, simply click on the Display Log File toolbar button ( ) in the TCL Console view. Object Type Prefixes There are number of different object types supported by ACE.
Creating an IP Configuration Chapter 4. Tasks Creating an IP Configuration Achronix FPGAs feature embedded IP to support clock signal generation (PLLs), FIFOs, DDR3, Ethernet, PCIe, and high-speed serial communication (SerDes). These highly flexible IP blocks require configuration for proper operation. ACE includes a number of IP Editors and Views which guide the user through the process of correctly configuring IP. The data for these IP configuration editing sessions is stored in .
Creating an IP Configuration Chapter 4. Tasks Setting the IP Configuration From the IP Editor, use either the Back and Next or the Outline view to navigate the editor pages, setting the appropriate values needed for the desired configuration. Any errors and warnings are displayed in the IP Problems view. Some IP Editors will also display supplemental graphical information in the IP Diagram view.
Viewing the Floorplanner Chapter 4. Tasks Viewing the Floorplanner Opening and Closing the Fly-Out Palette To open and close the Floorplanner view’s fly-out palette of view options: 1. Click on the Fly-out button ( ) on the far right side of the Floorplanner view to open the fly-out palette. Note: While the fly-out palette is open, it may be resized by clicking and dragging its left border. 2. Once the view options are configured, click on the Fly-in button ( palette to close the fly-out palette.
Viewing the Floorplanner Chapter 4. Tasks Panning To pan with the scroll bars: • Click and drag the vertical scroll bar to pan up and down or click and drag the horizontal scroll bar to pan left and right. • In Linux, place the mouse cursor over a scroll bar, then roll the mouse wheel. To pan with key-strokes: • Use the ARROW keys on the keyboard to pan left, right, up and down. • To scroll faster, press the Ctrl key while pressing the ARROW keys. To pan with the Placement Tool: 1.
Viewing the Floorplanner Chapter 4. Tasks 1. Select the Selection Tool ( ) from the view toolbar. From the Selection section fly-out palette, check the object types to deselect. 2. Press and hold the ’d’ key on the keyboard to start a selection rectangle at the current mouse position to deselect the objects. 3. Drag the mouse while holding down the key to create a selection rectangle including the objects to deselect.
Viewing the Floorplanner Chapter 4. Tasks Viewing Object Labels A variety of object labels are available when displaying objects in the Floorplanner view (see ”Fly-Out Palette”). To display object labels in the Floorplanner view: 1. In the Labels ( ) section of the fly-out palette, select which object labels to display. 2. Pan and zoom to objects of interest to view the object labels. Note: Some labels do not show up unless the view is zoomed in far enough to display the extent of the text.
Viewing the Package Layout Chapter 4. Tasks Viewing the Package Layout Opening and Closing the Fly-Out Palette To open and close the Package view’s fly-out palette of view options: 1. Click on the Fly-out button ( ) on the far right side of the Package view to open the fly-out palette. Note: While the fly-out palette is open, it may be resized by clicking and dragging its left border. 2. Once the view options are configured, click on the Fly-in button ( palette to close the fly-out palette.
Viewing the Package Layout Chapter 4. Tasks Panning To pan with the scroll bars: 1. Click and drag the vertical scroll bar to pan up and down or click and drag the horizontal scroll bar to pan left and right. To pan with key-strokes: 1. Use the ARROW keys on the keyboard to pan left, right, up and down. To pan with the Placement Tool: 1. Select the Placement Tool ( ) from the view toolbar. 2. Hover over any point in the Package view which shows the Pan cursor ( with the mouse to pan around. ).
Viewing the Package Layout Chapter 4. Tasks 1. Select the Selection Tool ( ) from the view toolbar. From the Selection section of the fly-out palette, check the object types to deselect. Also, ensure the Action control is set to Deselect. 2. Click and drag with the left mouse button in the view to create a selection rectangle. Then, release the mouse button to remove the objects from the current selection set. Toggling Mouse Tools To toggle the mouse tools: 1.
Viewing the Package Layout Chapter 4. Tasks Getting Object Tooltips For instant feedback on instance or site names in the Package view, a tooltip (hover text) can be enabled. In addition, the contents of the tooltip can be printed to the Tcl Console view for easy copy and paste. To get object tooltip text: 1. In the Tool Tip Text ( ) section of the fly-out palette, check the object types to get tool tip text for. 2. In the Package view, hover over objects to display tool tip text.
Pre-Placing a Design Chapter 4. Tasks Pre-Placing a Design Placing an Object Currently in ACE, there are two types of objects that can be placed: instances and ports. Placing a port is equivalent to placing the pad or macro instance that the port is connected to in the design. There are two types of placement in ACE: soft and fixed. Fixed placement locks the placement of an instance to a site such that the placer is not allowed to move the instance to another site.
Pre-Placing a Design Chapter 4. Tasks Changing Between Fixed and Soft Placement There are two types of placement in ACE: soft and fixed. Fixed placement locks the placement of an instance to a site such that the placer is not allowed to move the instance to another site. Fixed placement is the only type of pre-placement command recommended. Soft placement is used as a global placement hint to the placer. Soft placement is not fully functional.
Pre-Placing a Design Chapter 4. Tasks Removing Placement To un-place objects with key-strokes: 1. In the Floorplanner view or Package view, press and hold the ’r’ key on the keyboard to start a selection rectangle at the current mouse position to remove placement of objects. 2. Drag the mouse while holding down the key to create a selection rectangle including the objects to be un-place. Release the key to un-place the objects. To un-place objects with the Selection Tool: 1. Select the Selection Tool ( 2.
Analyzing Critical Paths Chapter 4. Tasks Analyzing Critical Paths Critical paths are computed by timing analysis. Timing analysis can be run at several points in the flow, as indicated in the Flow view. Timing analysis can be repeated with different implementation options without having to re-run the rest of the flow, by double-clicking the appropriate Run . . . Timing Analysis flow step.
Analyzing Critical Paths Chapter 4. Tasks • Asynchronous devices: By default, highlight colors are arranged in a gradient from red to yellow according to frequency. The lowest frequencies will always be colored red by default, even if they meet timing. 3. To highlight a path in the Floorplanner, simply check the box for the desired path in the Highlight column of the table within the Critical Paths view. To un-highlight a path, simply uncheck the box.
Analyzing Critical Paths Chapter 4. Tasks The nets are now added to the selection in the Selection view and are shown with the selection color in the Floorplanner view. Zooming to Critical Paths To zoom the Floorplanner view to a critical path’s region: 1. In the Critical Paths view, click on the table row containing the desired critical path data. 2. To zoom to the path in the Floorplanner view, click on the Zoom to Path toolbar button ( Critical Paths view toolbar.
Analyzing Critical Paths Chapter 4. Tasks hidden due to insufficient drawing area. Arrows The arrows connecting the graph nodes in the diagram represent the nets connecting the object instances. They too can display various pieces of information that may be enabled and disabled via the flyout palette. In addition to the arrow’s direction, the line types making up the arrow also represent important information.
Analyzing Critical Paths Chapter 4. Tasks Figure 4.9: Critical Path Diagram View for Loop Reconvergent critical paths (which only occur in asynchronous fabrics) are potentially the most complicated - these have multiple possible graphical representations, selectable by changing options in the Layers section of the Critical Path Diagram view’s fly-out palette. The ”RC Path Topology” settings alter the arrangement of the Nodes in the graph.
Analyzing Critical Paths Chapter 4. Tasks Figure 4.10: Reconvergent Path diagram configured with Driver->Sink topology, User Logic arrows, and no Intermediate Nodes Figure 4.11: Reconvergent Path diagram configured with Driver->Sink topology, Data Flow arrows, and no Intermediate Nodes When the topology is set to Polygon, the same nodes are arranged so that the nodes are in a balanced polygon, like a square, pentagon, hexagon, octagon, etc. 277 http://www.achronix.com UG001 Rev. 5.
Analyzing Critical Paths Chapter 4. Tasks Figure 4.12: Reconvergent Path diagram configured with Polygon topology, User Logic arrows, and no Intermediate Nodes UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.
Analyzing Critical Paths Chapter 4. Tasks Figure 4.13: Reconvergent Path diagram configured with Polygon topology, Data Flow arrows, and no Intermediate Nodes 279 http://www.achronix.com UG001 Rev. 5.
Analyzing Critical Paths Chapter 4. Tasks When comparing the four screenshots above, it is also possible to see the differences between the ”RC Path Arrows” settings of User Logic and Data Flow. What may not be obvious from the diagrams above is that each DFF is driving two LUT4s with a single net. This only becomes obvious when the Intermediate Nodes setting is enabled, and the net names become visible.
Analyzing Critical Paths Chapter 4. Tasks Figure 4.15: Critical Path Diagram with net ”s[30]” selected. Note that the single net is represented by two arrows. Viewing Critical Paths in the Schematic Viewer Currently, ACE does not have its own built-in schematic viewer. Viewing critical paths must be done in the synthesis tool. In order to facilitate this, ACE can optionally generate a Tcl script with find commands for objects along each critical path. To view critical paths in the synthesis tool: 1.
Managing I/Os Chapter 4. Tasks Managing I/Os I/O electrical properties are often iteratively tweaked at the final stages of design. Frequently the user does not want to alter their source RTL to make these changes, because doing so would necessitate re-running the entire Flow. The IO Assignment view was created to ease these last-minute tweaks. This view allows I/O electrical changes to be made without impacting the PnR.
Running the SnapShot Debugger Chapter 4. Tasks Running the SnapShot Debugger SnapShot is the real-time design debugging tool for Achronix FPGAs. SnapShot, which is embedded in the ACE Software, delivers a practical platform to evaluate the signals of a user’s design in real-time, and optionally send stimuli to the user’s design. To utilize the SnapShot debugger tool, the SnapShot macro must be instantiated inside the RTL for the Design-Under-Test (DUT).
Running the SnapShot Debugger Chapter 4. Tasks The following sections will further explain SnapShot and guide the user through the process. General SnapShot Description and Architecture The SnapShot macro samples user-signals in real time, and sends the captured data back through the JTAG interface. The macro may also optionally send stimulus to the Design-Under-Test.
Running the SnapShot Debugger Chapter 4. Tasks Figure 4.18: SnapShot Trigger Detector Block Diagram • Trace Buffers Trace Buffers are implemented using 2048×36 Block-RAMs (BRAM80K). The BlockRAMs (BRAM80K) are used to capture user data with respect to the user clock, and in turn this data can be read serially through the JTAG. The number of BRAMs used will vary based upon the data width selected by the user.
Running the SnapShot Debugger Chapter 4. Tasks Rstn out Output usr clk When low, indicates SnapShot logic is being reset. May be used to reset portions of user’s design, if design utilizes Stimuli. This output may safely be left floating. Arm Output usr clk Indicates SnapShot logic has been armed. When high, the value in Stimuli is valid. Does not indicate whether SnapShot is sampling (may stay high after sampling is complete.) Will deassert when Rstn out is active.
Running the SnapShot Debugger Chapter 4. Tasks The user may optionally modify their Design Under Test (DUT) to respond to external data sent via the SnapShot interface. The Rstn out, Arm, and Stimuli signals may be used to create desired events, which may then be observed in the trace buffers. If any of these outputs are used, then the OUTPUTPIPELINING parameter value will usually need to be increased above its default value of 0.
Running the SnapShot Debugger 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Chapter 4. Tasks wire arm ; / / / / / S i g n a l i n d i c a t e s SnapShot i s armed ( and has s t a r t e d t e s t i n g p a t t e r n s ) //////// Now SnapShot macro b l o c k i n s t a n t i a t i o n /////// ACX SNAP SHOT # ( . MNTR WIDTH(MNTR WIDTH) , .DUTNAME(DUTNAME) , . OUTPUTPIPELINING ( OUTPUTPIPELINING ) ) snapshot instance ( . tck ( tck ) , . tms ( tms ) , .
Running the SnapShot Debugger 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Stimuli Rstn out Arm ) ; end component ; Chapter 4.
Running the SnapShot Debugger Chapter 4. Tasks The Automatically Detect Pod option is a convenience for when there is only one pod connected. If more than one pod is automatically detected, the user must specify exactly which pod should be used. The Specify Pod Name option allows the user to supply a comma-delimited list of one or more pod names13 .
Running the SnapShot Debugger Chapter 4. Tasks Each sequential trigger is configured in 2 parts: the ”Pattern” and the ”Dont Care” mask. The trigger ”Pattern” defines the binary value of each of the 36 monitor channel signals that is required to detect a match. The trigger ”Dont Care” mask defines which of the 36 monitor channels to ignore when computing a match. If a ”Dont Care” bit is set to 1, then the corresponding signal will be ignored in the trigger match comparison.
Running the SnapShot Debugger Chapter 4. Tasks Setting Triggering Range In the SnapShot Debugger view, the ”Pre-Store” setting configures the how many samples are collected before the trigger, and (indirectly) how many are collected after the trigger. (Reminder: SnapShot always collects 1024 samples.
Running the SnapShot Debugger Chapter 4. Tasks Activating SnapShot Once all the fields in the SnapShot Debugger view are configured, and the design is running on the target device, SnapShot is ready to be activated. Select the Arm button (or the Arm SnapShot ( ) button in the SnapShot Debugger view’s toolbar), and the SnapShot debugging tool will begin to analyze the already-executing design in real-time.
Playing a STAPL File Chapter 4. Tasks Playing a STAPL File A STAPL14 file can be run or played from the Download view. From this view, individual STAPL Actions can be selected for playing. The software also allows for individual STAPL Procedures to be selected/deselected. To access the Download view, select Window → Show View → Others → Download View. Note: For details on connecting to Bitporter JTAG pods, Bitporter pod naming, and STAPL Actions and Procedures, see the Bitporter User Guide (UG004).
Optimizing a Design Chapter 4. Tasks Optimizing a Design There are numerous methods of design optimization available to ACE users. Many optimizations are able to be performed automatically by ACE, at the cost of additional runtime. These automatic optimizations are managed at a granular level through the Implementation Options, which may be configured from the Options View and/or the Tcl command set impl option.
Optimizing a Design Chapter 4. Tasks Generating Option Set Implementations and Starting Background Execution After the Start Selected button has been pressed, but before the behavior described in Starting Background Execution commences, ACE will: 1. remove implementations in the active project with the same name as to-be-generated implementations 2. create new implementations (exact copies of the template implementation) with the required names 3.
Placement Regions and Placement Region Constraints Chapter 4. Tasks Placement Regions and Placement Region Constraints Placement Regions and Placement Region Constraints are an advanced feature, and should only be used under the guidance of an Achronix FAE. Unguided use of placement region constraints can cause loss of QOR, and may make a design impossible for the Placer or Router to solve.
Placement Regions and Placement Region Constraints Chapter 4. Tasks 7. Fill in the desired Placement Region name 8. Select whether the Placement Region should be based upon the simpler Clock Regions, or the more granular subtiles. 9. Press the ”Finish” button to create the new Placement Region. 10. ACE adds the new Placement Region to the table in the Placement Regions view and displays it as a translucent overlay within the Floorplanner. (At this point, the region will contain no constraints.
Placement Regions and Placement Region Constraints Chapter 4. Tasks 4. (Optional) If the Placement Region is meant to align with (snap to) one or more Clock Regions, enable the overlay for those regions from the Clock Regions view. This will not affect the functionality during the resize in any way, but will make it easier to know where to define the region bounds. 5. Move the mouse over the placement region to be moved.
Placement Regions and Placement Region Constraints Chapter 4. Tasks the Instances/Paths not in the current set of 200 on the visible page of results) may be drag-assigned. • the Critical Paths view, where individual Paths or groups of paths may be drag-assigned. • the Netlist Browser view, where any node of the tree may be dragged, and all child nodes will be included. Even the Clock Domain nodes may be dragged, to include all applicable Instances from that clock domain in the assignment.
Placement Regions and Placement Region Constraints Important consideration when saving placement region constraints: Chapter 4. Tasks Only the final list of all individual instances being constrained is saved. The individual Tcl commands which built up the final list of constraints (including ’find’ commands, the extraction of instances from Critical Paths, or from Clock Domains) is lost.
add project netlist Chapter 5. Tcl Command Reference Tcl Command Reference add project constraints add project constraints [-project ] This command adds a link to an SDC constraint file to a project. Argument Required/Optional Description Required The required argument is used to specify the file path to the SDC constraint file.
all clocks Chapter 5.
clear drawing Chapter 5. Tcl Command Reference following commands can be entered on the command line *before* the final flow step: set_extra_pipeline -xp 5 clk1 set_extra_pipeline -xp 5 clk7 apply_extra_pipeline Note: It is an error to run this command after the post-processing flow step. Important Caveat: Failure to run this command after an XP (eXtra Pipeline) value was changed will cause a changed XP value to be ignored in Bitstream Generation and in the expanded verilog output files.
clear ovals [-id ] Chapter 5. Tcl Command Reference Optional The optional -id option specifies a unique id for a single line to clear. If this option is not used, all lines will be cleared. clear ovals clear ovals [-id ] This command allows you to clear a custom oval or all the ovals on the GUIs layout view. Argument Required/Optional Description [-id ] Optional The optional -id option specifies a unique id for a single oval to clear.
clock info Chapter 5. Tcl Command Reference clear polygons clear polygons [-id ] This command allows you to clear a custom polygon or all the polygons on the GUIs layout view. Argument Required/Optional Description [-id ] Optional The optional -id option specifies a unique id for a single polygon to clear. If this option is not used, all polygons will be cleared.
clock relation Chapter 5.
create flow step Chapter 5. Tcl Command Reference same units as T). By default the numbers are as small as possible, but with -group all related clocks use the same units.
create generated clock Chapter 5. Tcl Command Reference [-parent id ] Optional The optional -parent id option specifies the flow step id of an existing flow step (which does not have a command of its own) that this new flow step will be grouped under in the flow hierarchy. [-required] Optional The optional -required option specifies whether or not this flow step is required for further processing of the flow.
create path Chapter 5. Tcl Command Reference This command is useful for the user to generate the clock constraint if the design has PLL or any circuitgenerated clock. In other words this command also represents an internal clock of the design. User must specify the correct master pin which is a source pin to generate this clock constraint. create impl create impl [-project ] [-copy] [-not active] This command creates a new implementation in a project.
create region Chapter 5. Tcl Command Reference create project create project [-impl ] [-not active] This command creates a new project in ACE. Argument Required/Optional Description Required The required argument is used to specify the project file location for the new project. The file name is used as the project’s name in ACE.
disable project constraints Chapter 5. Tcl Command Reference Optional [-batch] Postpone application of this constraint until apply placement is called (this avoids frequent GUI updates). This option is only relevant if you manually apply placement constraints after the design has been prepared. deselect deselect [-objects ] This command removes objects from the current list of selected objects.
draw arc Chapter 5. Tcl Command Reference [-impl ] Optional The optional -project and -impl options are used to specify an alternate project implementation (by name) to disable constraints for. Required The project constraints file to disable for a project implementation. display file display file This command automatically opens a file in the GUI. This command has no effect in batch mode.
draw arc Chapter 5. Tcl Command Reference Required The required argument specifies the width of the arc. Required The required argument specifies the height of the arc. Required The required argument specifies the starting angle of the arc. Required The required argument specifies the angle of the arc. [-layer ] Optional The optional -layer option specifies the drawing layer for the arc.
draw line Chapter 5. Tcl Command Reference draw line draw line [-layer ] [-id ] [-rgb ] [-batch] [-thickness ] This command allows you to draw a custom line on the GUIs layout view. Argument Required/Optional Description Required The required argument specifies the first x coordinate for the line. Required The required argument specifies the first y coordinate for the line.
draw oval Chapter 5. Tcl Command Reference draw oval draw oval [-layer ] [-id ] [-rgb ] [-batch] [-thickness ] [-fill] This command allows you to draw a custom oval on the GUIs layout view. Argument Required/Optional Description Required The required argument specifies the upper-left x coordinate for the oval. Required The required argument specifies the upper-left y coordinate for the oval.
draw polygon [-fill] Chapter 5. Tcl Command Reference Optional The optional -fill option specifies whether the oval should be filled with color or not. If this option is not used, the oval will be hollow. draw polygon draw polygon [-layer ] [-id ] [-rgb ] [-batch] [-thickness ] [-fill] This command allows you to draw a custom polygon on the GUIs layout view.
draw rectangle [-fill] Chapter 5. Tcl Command Reference Optional The optional -fill option specifies whether the arc should be filled with color or not. If this option is not used, the arc will be hollow. draw rectangle draw rectangle [-layer ] [-id ] [-rgb ] [-batch] [-thickness ] [-fill] This command allows you to draw a custom rectangle on the GUIs layout view.
draw string Chapter 5. Tcl Command Reference [-thickness ] Optional The optional -thickness option specifies the rectangle thickness in pixels. If this option is not used, a thickness of 1 will be used. [-fill] Optional The optional -fill option specifies whether the rectangle should be filled with color or not. If this option is not used, the rectangle will be hollow.
find Chapter 5. Tcl Command Reference Optional [-batch] The optional -batch option causes the GUI to not refresh after this command. This is useful when running many draw commands in a row. Afterwards, refresh drawing can be called. enable flow step enable flow step This command enables an existing optional flow step to be run during a ”run” command. Argument Required/Optional Description Required The required argument specifies the id of the flow step to enable.
find Chapter 5. Tcl Command Reference Argument Required/Optional Description Required The required argument specifies a list of pattern strings to match object names against. Each pattern string in the list may use ’*’ and ’?’ wildcard characters for matching. [-insts] Optional The optional -insts object type option is used to specify that the results may include instance object types.
find Chapter 5. Tcl Command Reference [-paths] Optional The optional -paths object type option is used to specify that the results may include path object types. If no other object type option is used, all object types will be included in the results by default. If another object type option is used, and the -paths option is not used, then the results will not contain any path objects.
get active impl Chapter 5. Tcl Command Reference generate ip design files generate ip design files This command generates the enabled design files for a given IP configuration (.acxip file). Argument Required/Optional Description Required The required argument specifies the IP configuration (.acxip file) to generate design files for.
get clocks Chapter 5. Tcl Command Reference current ACE session. Argument Required/Optional Description [-quiet] Optional do not print a message if there is no active project get cells get cells filter [-no case] [-compatibility mode] Returns a collection of cells (instances) in the design. All cell names match the specified pattern. Wildcards may be used to select multiple cells at once.
get enabled constraints Chapter 5. Tcl Command Reference Elaboration This command is especially useful for the user to see how many clocks exist inside the design. This feature allows a wild card filter also. This command works after the design has passed through the Run Prepare flow step (run prepare). User can insert this command from ACE TCL shell window or use inside the SDC file.
get impl names Chapter 5. Tcl Command Reference [-project ] Optional The optional -project and -impl options are used to specify an alternate project implementation (by name) to get enabled constraints for. [-impl ] Optional The optional -project and -impl options are used to specify an alternate project implementation (by name) to get enabled constraints for.
get nets Chapter 5. Tcl Command Reference get impl option get impl option
get part names Chapter 5. Tcl Command Reference filter Required The required option is used to filter returned node names (string patterns are matched using Tcl string matching) [-no case] Optional The optional -no case option specifies the matching of node names to the filter should be case-insensitive get part names get part names This command returns the list of valid part names in the installed library.
get placement Chapter 5. Tcl Command Reference [-slack] Optional The optional -text option returns the details text for this path. [-tokens] Optional The optional -text option returns the details text for this path. get pins get pins filter [-no case] [-compatibility mode] Returns a collection of pins in the design. All pin names match the specified pattern. Wildcards may be used to select multiple pins at once.
get project directory Chapter 5. Tcl Command Reference get pod names get pod names [-all] [-usb] [-ethernet] [-list ] Returns a list of names of available Bitporter pods. Argument Required/Optional Description [-all] Optional (default behavior) returns USB and detected Ethernet pods. [-usb] Optional (optional) returns only the USB pods. [-ethernet] Optional (optional) returns only the detected Ethernet pods.
get properties Chapter 5. Tcl Command Reference This command returns the path to a project file’s parent directory Argument Required/Optional Description [-project ] Optional The optional -project option is used to specify an alternate project (by name) to get the directory path from. get project ip files get project ip files [-project ] This command returns a list of all the IP settings file paths for a project.
get selection Chapter 5. Tcl Command Reference get property get property
get stapl actions Chapter 5. Tcl Command Reference [-ports] Optional The optional -ports object type option is used to specify that the results may include primary IO port object types. If no other object type option is used, all object types will be included in the results by default. If another object type option is used, and the -ports option is not used, then the results will not contain any primary IO port objects.
get techlibt name Chapter 5. Tcl Command Reference get techlib name get techlib name This command returns the name the of black box verilog library for the given part. Argument Required/Optional Description Required The required argument is used to specify the name of the part to find the library for. The part name specified must exist among the valid part names in the ACE installation.
get techlibx path Chapter 5. Tcl Command Reference Required The required argument is used to specify the name of the part to find the library for. The part name specified must exist among the valid part names in the ACE installation. get techlibt path get techlibt path This command returns the path to the transmuted black box verilog library file for the given part.
load place and route Chapter 5. Tcl Command Reference highlight highlight [-rgb ] [-batch] This command is used to highlight or un-highlight a list of objects in the GUI’s physical view. Argument Required/Optional Description Required The required argument is used to specify a list of objects to set the highlight color for. Highlight instance, net, and path object types is currently supported. All other object types passed in will be silently ignored.
message Chapter 5. Tcl Command Reference [-acxfile ] Optional The required -acxfile option is specifies the place and route data file to load. [-reportsdir ] Optional The optional -reportsdir option is used to override the default location for report files during this step. Usage Notes: Use of this command is now discouraged. The Tcl commands save impl and restore impl should be used instead.
remove impl Chapter 5. Tcl Command Reference [-info] Optional Make this message an informational message. [-warning] Optional Make this message a warning message. [-error] Optional Make this message an error message. prepare sta prepare sta [-fold rise fall] Prepare synchronous timing analysis for interactive use. Argument Required/Optional Description [-fold rise fall] Optional Remove some rise/fall paths from the analysis to reduce duplicates.
remove project ip Chapter 5. Tcl Command Reference remove path remove path This command removes a user-defined pin path. Argument Required/Optional Description Required The required argument specifies the id of the path to remove. remove project remove project This command removes a project from ACE. The project file on disk is not deleted.
remove region insts [-project ] Chapter 5. Tcl Command Reference Optional The optional -project option is used to specify an alternate project (by name) for the IP settings file to be removed from. remove project netlist remove project netlist [-project ] This command removes the link to a verilog netlist file from a project. The verilog netlist file on disk is not deleted.
report clock Chapter 5. Tcl Command Reference rename impl rename impl [-project ] [-impl ] This command renames an implementation. Changing the name of an implementation also changes the name of the implementation output directory on disk (even without calling ”save project”). Argument Required/Optional Description Required The required argument is used to specify the new implementation name.
report pins Chapter 5. Tcl Command Reference [-outputfile ] Optional The optional -outputfile option may be used to specify an output file name or file path. If this option is not present, the output is written to the default implementation reports directory and is named impl options.html. [-text] Optional The optional -text option is used to specify whether the file should be output as plain text.
report power Chapter 5. Tcl Command Reference [-outputfile ] Optional The optional -outputfile option may be used to specify an output file name or file path. If this option is not present, the output is written to the default implementation reports directory and is named pins.html. [-text] Optional The optional -text option is used to specify whether the file should be output as plain text.
report regions Chapter 5. Tcl Command Reference [-clocks ] Optional The -clocks < clk1 freq clk2 freq .. clkn freq > option may be used to specify the operating frequency of all the clocks in the design. If this option is not present, the frequencies from the design constraints will be used by default. If no constraints are found, the best achieved frequency will be used [-outputfile ] Optional The optional -outputfile option may be used to specify an output file name or file path.
report utilization [-csv] Chapter 5. Tcl Command Reference Optional The optional -csv option is used to specify whether the file should be output as a CSV file for use in Excel spreadsheets. report routing report routing [-outputfile ] [-text] [-csv] [-nonterse] [-terse] [-overflowreportlimit ] [-verbose] This command generates and writes a formatted routing report.
reset sta Chapter 5. Tcl Command Reference [-text] Optional The optional -text option is used to specify whether the file should be output as plain text. [-csv] Optional The optional -csv option is used to specify whether the file should be output as a CSV file for use in Excel spreadsheets. reset impl option reset impl option
restore project Chapter 5. Tcl Command Reference restoring an impl.
run fanout control Chapter 5. Tcl Command Reference [-activeimpl ] Optional The -activeimpl option can be used to specify an alternate impl name to activate and restore. By default, the last active impl during the session the project was saved in will be activated. [-acxdb ] Optional Specifies an ACXDB file path to restore the state of the active impl from [-force] Optional The -force option can be used to override a project lock that has been set by another ACE session.
run gate balance [-fanout limit clone ] Chapter 5. Tcl Command Reference Optional Apply fanout cloning on nets with fanout greater than this limit run final drc checks run final drc checks [-reportsdir ] [-debugdir ] This command performs final DRC checks on the design.
run generate bitstream Chapter 5. Tcl Command Reference run generate bitstream run generate bitstream [-outputdir ] [-reportsdir ] [-debugdir ] [-chainfile ] [-aeskey ] [-monitor delay count ] [-flash] [-flash4x] [-hex] [-cpu] [-compress] [-nocompress] This command generates a bitstream file for programming the target device.
run insert reset Chapter 5. Tcl Command Reference run generate netlist run generate netlist [-outputfile ] [-debugdir ] [-final] [-compress] This command generates a verilog netlist for simulation. Argument Required/Optional Description [-outputfile ] Optional Output netlist file name. [-debugdir ] Optional The optional -debugdir option is used to override the default location for debug files during this step.
run prepare Chapter 5. Tcl Command Reference [-structural clustering ] Optional Turn on structural clustering during placement (1,0) [-verbose ] Optional Produce extra reports and intermediate results (1,0) [-incremental] Optional Run placement in incremental mode run post process run post process [-reportsdir ] [-debugdir ] This command post-processes the routed design to insert reset and other Achronix-specific technologies.
run remove reset Chapter 5. Tcl Command Reference [-constraints ] Optional The optional -constraints option overrides the list of SDC constraint files to use during this step. [-netlists ] Optional The optional -netlists option overrides the list of verilog netlist files to use during this step.
run timing analysis Chapter 5. Tcl Command Reference [-nocore] Optional Non-core routing only [-timing ] Optional Use timing-driven routing (1, 0) run stapl action run stapl action [-pod list ] [-disabled procs ] [-enabled procs ] [-log file ] This command executes the given stapl program action. Argument Required/Optional Description Required (required) specifies which STAPL file will contain the Action to be run.
run un post process Chapter 5. Tcl Command Reference [-prepared] Optional Indicates that the design has only been prepared (this is the default) [-placed] Optional Indicates that the design has been placed but not routed [-routed] Optional Indicates that the design has been placed and routed [-final] Optional Indicates that this is sign-off timing (this involves some extra checks) [-name postfix ] Optional Postfix added to report file name (e.g.
save placement Chapter 5. Tcl Command Reference [-constants] Optional Just unplace constant sources [-insts ] Optional unplace only the instances specified in this list [-unplacefixedpins] Optional unplace pins of fixed instances run unroute run unroute [-net ] [-pin ] [-nets ] [-nocore] [-keepsametile] [-uniqify] [-consts] [-HD] [-noHD] Remove all or parts of a routing.
save placement Chapter 5. Tcl Command Reference Argument Required/Optional Description [-iofile ] Optional The optional -iofile option is used to specify the file path to save the IO pre-placement commands to. If this option is not used, the file will be saved to the active project’s directory as io preplacement.pdc [-corefile ] Optional The optional -corefile option is used to specify the file path to save the Core pre-placement commands to.
save project Chapter 5. Tcl Command Reference Optional [-ball names] The optional -ball names option is used to specify whether ball names should be output for IO Buffers instead of site names. save impl save impl [-no log] The save impl command always works on the active impl, since the active impl is connected to the DB state. All other impls have no DB state. The save impl command saves the state of an impl (impl options and db state) to a .acxdb file. By default, the .
select [-no log] Chapter 5. Tcl Command Reference Optional If the -no log option is set, no additional debug information will be saved in the ACXDB file, including log files from the current ACE session save properties save properties [-outputfile ] [-add] [-port names] This command is used to save all changed properties on objects in the DB after prepare has been run.
set clock groups Chapter 5. Tcl Command Reference Argument Required/Optional Description Required The required argument specifies a list of objects to append to the current selection. Objects must be prepended with object type prefixes (see ”find” command). See also: Object Type Prefixes, Selection View, find, Search View set active impl set active impl [-project ] This command sets the active implementation for the current ACE session.
set cluster Chapter 5. Tcl Command Reference Elaboration This command takes a list of clocks and makes them unrelated to each other. Below is the command how to use this command inside the SDC file: set_clock_groups group {clock1 clock2 clock3} This command makes clock1, clock2 and clock3 unrelated to all other clocks, but not to each other.
set extra delay Chapter 5. Tcl Command Reference Optional [-wt ] Optional 2nd level cluster weight 2, . . . , 5 - higher weights signify cluster importance This clustering command directs the placer to keep the instances (listed in the command) together. For loops and long paths of reconvergent paths, the tool knows to focus on placing these instances together, yielding better results.
set extra pipeline Chapter 5. Tcl Command Reference To add additional delays on any pin in , a leading delay value can be added in the , like so: 1 : = ’ { ’ pin1 2 , pin2 3 , pin3 ’ } ’ The above directive requires the run gate balance command to insert 1 buffer delay for pin1, 2 delays for pin2, and 3 delays for pin3. Buffer sharing is on by default. In the above example, only 3 buffers will be inserted.
set impl option Chapter 5. Tcl Command Reference Argument Required/Optional Description clock Required Specify clock domain [-xp ] Optional Extra pipelining amount (>=0) [-cdc ] Optional Extra pipelining added at each crossing from another (unrelated) domain into this domain Note: If this command is executed after run prepare (the Run Prepare flow step), apply extra pipeline command must be run as well to apply the changes. apply extra pipeline for more information.
set impl option Chapter 5. Tcl Command Reference Argument Required/Optional Description
set input transition Chapter 5.
set output delay Chapter 5.
set placement Chapter 5. Tcl Command Reference or in easier way user can use for loop in SDC file for {set i 0} {$i < } {incr i} { set_output_delay 0 -combinational } For example in user design an output pins (abus [18:0]) are defined as 19-bit bus. Instead of using 19-line with bit-split user can use this above sample.
set region bounds [-batch] Chapter 5. Tcl Command Reference Optional Postpone application of this constraint until apply placement is called (this avoids frequent GUI updates). This option is only relevant if you manually apply placement constraints after the design has been prepared. set property set property [-quiet] This command is used to set properties on objects in the DB.
write bitstream Chapter 5. Tcl Command Reference set units set units Set the default units for timing constraints.
write netlist Chapter 5.
write tcl history Chapter 5. Tcl Command Reference [-debugdir ] Optional The optional -debugdir option is used to override the default location for debug files during this step.
Chapter 6. Revision History Revision History The following outline lists the revision history of this document. Version 5.0.0: • Updated to match ACE 5.
Chapter 6. Revision History * Updated the Search view, Selection view, and Netlist Browser View to mention new dragand-drop support for assignment of placement region constraints – Updated the Netlist Browser View to discuss the now-asynchronous tree population to avoid performance issues with massive designs – Updated Selection view to mention new capability to initiate drag-and-drop operations with branch nodes to use all selected objects (even beyond the current 200) of that type.
Chapter 6. Revision History * added: add region insts, create region, display rtl, get region insts, remove region, remove region insts, report regions, reset impl option, save regions, set clock type, set flyline direction, set region bounds, write tcl history * run chiptap was renamed run snapshot • Updates to match ACE 4.2.1, 4.2.2, & 4.2.
Chapter 6. Revision History * now obsolete/deprecated: run auto cst ideal reset, initialize flow, load flowscripts, • Updated to match ACE 4.
Revision History Speedster22i FPGA Family – Updated the Download View and Selecting A STAPL File pages to mention the new MRU list/combo-box storing the last 15 *.jam files used. – Updated the Multiprocess View and Running Multiple Flows in Parallel to cover the new ”Multiprocess Flow Management” section. Also enhanced the guidelines for optimal settings of the Parallel Job Count: field.
