User manual

Bit 2 determines the number of stop bits. There can be either one or two stop bits. If Bit 2 is set
to 0, there will be one stop bit. If Bit 2 is set to 1, there will be two stop bits.
Bits 3 through 6 control parity and break enable. They are not commonly used for
communications and should be set to zeroes.
Bit 7 is the DLAB discussed earlier. It must be set to zero after the divisor is loaded or else there
will be no communications.
The C command to set the UART for an 8-bit word, no parity, and one stop bit is:
outportb(BASEADDR +3, 0x03)
The third step of the initialization sequence is to set the Modem Control Register at Base Address +4.
This register controls functions on some boards. Bit 1 is the Request to Send (RTS) control bit. This bit
should be left low until transmission time. (Note: When operating in the automatic RS485 mode, the
state of this bit is not significant.) Bits 2 and 3 are user-designated outputs. Bit 2 may be ignored on this
board. Bit 3 is used to enable interrupts and should be set high if an interrupt-driven receiver is to be
used.
The final initialization step is to flush the receiver buffers. You do this with two reads from the receiver
buffer at Base Address +0. When done, the UART is ready to use.
Reception
Reception can be handled in two ways: polling and interrupt-driven. When polling, reception is
accomplished by constantly reading the Line Status Register at Base Address +5. Bit 0 of this register is
set high whenever data are ready to be read from the chip. Polling is not effective at high data rates
above because the program cannot do anything else when it is polling or data could be missed. The
following code fragment implements a polling loop and uses a value of 13, (ASCII carriage return) as an
end-of-transmission marker:
do
{
while (!(inportb(BASEADDR +5) & 1)); /*Wait until data ready*/
data[i++]= inportb(BASEADDR);
}
while (data[i]!=13); /*Reads the line until null character rec'd*/
Interrupt-driven communications should be used whenever possible and is required for high data rates.
Writing an interrupt-driven receiver is not much more complex than writing a polled receiver but care
should be taken when installing or removing your interrupt handler to avoid writing the wrong interrupt,
disabling the wrong interrupt, or turning interrupts off for too long a period.
The handler would first read the Interrupt Identification Register at Base Address +2. If the interrupt is
for Received Data Available, the handler then reads the data. If no interrupt is pending, control exits the
routine. A sample handler, written in C, is as follows:
readback = inportb(BASEADDR +2);
if (readback & 4) /*Readback will be set to 4 if data are available*/
data[i++]=inportb(BASEADDR);
outportb(0x20,0x20); /*Write EOI to 8259 Interrupt Controller*/
return;
Manual 104-ICOM-2S, 104-COM-2S 20