TM7300 Series Notebook Computer Service Guide PART NO.: 49.42A01.001 DOC. NO.
Copyright Copyright 1998 by Acer Incorporated. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without the prior written permission of Acer Incorporated.
About this Manual Purpose This service guide aims to furnish technical information to the service engineers and advanced users when upgrading, configuring, or repairing the TM7300 series notebook computer. Manual Structure This service guide contains technical information about the TM7300 series notebook computer. It consists of three chapters and five appendices. Chapter 1 System Introduction This chapter describes the system features and major components.
Appendix D Schematics This appendix contains the schematic diagrams for the system board. Appendix E BIOS POST Checkpoints This appendix lists and describes the BIOS POST checkpoints. Conventions The following are the conventions used in this manual: Text entered by user Represents text input by the user. Screen messages Denotes actual messages that appear onscreen. , , , etc. Represent the actual keys that you have to press on the keyboard.
Table of Contents Chapter 1 1.1 Features .............................................................................................................. 1-1 1.1.2 1.2 System Introduction FlashStart Automatic Power-On ............................................................ 1-2 Ports .................................................................................................................... 1-3 1.2.1 Rear Panel Ports............................................................................
1.7 1.6.14 PCMCIA...............................................................................................1-35 1.6.15 Parallel Port .........................................................................................1-36 1.6.16 Serial Port............................................................................................1-36 1.6.17 Touchpad.............................................................................................1-36 1.6.18 SIR/FIR............................
2.5 2.6 2.7 2.8 2.9 2.4.3 Pin Diagram .........................................................................................2-40 2.4.4 Pin Descriptions ...................................................................................2-41 Philips 87C552 System Management Controller .................................................2-43 2.5.1 Features...............................................................................................2-43 2.5.2 Block Diagram .........................
3.3 3.4 3.5 3.6 Advanced System Configuration...........................................................................3-5 3.3.1 Internal Cache........................................................................................3-5 3.3.2 External Cache ......................................................................................3-5 3.3.3 Enhanced IDE Features .........................................................................3-5 3.3.4 Onboard Communication Ports ...............
4.9 4.8.1 Detaching the Lower Housing from the Inside Assembly ......................4-14 4.8.2 Detaching the Upper Housing from the Inside Assembly ......................4-15 4.8.3 Removing the Touchpad ......................................................................4-16 4.8.4 Removing the Main Board....................................................................4-16 Disassembling the Display ..................................................................................
List of Figures x 1-1 Lid Switch .............................................................................................................1-2 1-2 Rear Port Location................................................................................................1-3 1-3 Left Port Location .................................................................................................1-4 1-4 Indicator Lights ..........................................................................................
4-8 Installing and Removing Memory......................................................................... 4-8 4-9 Removing the Display Hinge Covers...................................................................4-10 4-10 Removing the Center Hinge Cover .....................................................................4-10 4-11 Lifting Out the Keyboard .....................................................................................
List of Tables xii 1-1 Rear Port Descriptions ..........................................................................................1-3 1-2 Left Port Descriptions............................................................................................1-5 1-3 Indicator Light Descriptions...................................................................................1-5 1-4 Hot Key Descriptions ............................................................................................
1-35 Battery Specifications .........................................................................................1-40 1-36 DC-DC Converter Specifications.........................................................................1-40 1-37 DC-AC Inverter Specifications ............................................................................1-41 1-38 AC Adapter Specifications ..................................................................................1-41 1-39 Environmental Requirements...
& K D S W H U System Introduction The computer is packed with features that make it as easy to work with as it is to look at. Here are some of the computer’s features: 1.1 Features PERFORMANCE • Intel Pentium II 266 MHz processor • 64-bit main memory and 512KB external (L2) cache memory • Large display in active-matrix TFT • PCI local bus video with 128-bit graphics accelerator • ® Flexible module bay (3.
• Ergonomically-positioned touchpad pointing device EXPANDABILITY • CardBus PC Card (PCMCIA) slots (two type II/I or one type III) with Zoomed Video port function • Mini-dock option with two CardBus PC Card slots (two type II/I or one type III) • USB port onboard • Upgradeable memory and hard disk 1.1.2 FlashStart Automatic Power-On The computer has no on/off switch. Instead it uses a lid switch, located near the center of the display hinge, that turns the computer on and off automatically.
1.2 Ports The computer’s ports allow you to connect peripheral devices to your computer just as you would to a desktop PC. The main ports are found on the computer’s rear panel. The computer’s left panel contains the computer’s multimedia ports and PC card slots. 1.2.1 Rear Panel Ports The computer’s rear panel contains the computer’s main ports and connectors as shown in the illustration below.
UNIVERSAL SERIAL BUS (USB) PORT The computer’s USB (Universal Serial Bus) port located on the rear panel allows you to connect peripherals without occupying too many resources. Common USB devices include the mouse and keyboard. FAST INFRARED (FIR) PORT The computer’s FIR (fast infrared) port located on the rear panel allows you to transfer data to IRaware machines without cables. For example, you can transfer data between two IR-capable computers, or send data to an IR-aware printer without using a cable.
Table 1-2 Left Port Descriptions Port Icon Connects to... PC Card slots Two type I/II PC Cards or one type III Card Microphone-in/ Line-in External microphone or line input device Speaker-out/ Line-out Amplified speakers or headphones PC CARD SLOTS The computer contains two PC card slots on the left panel that accommodate two type I/II or one type III PC card(s). Consult your dealer for available PC card options.
1.2.4 Hot Keys The computer’s special Fn key, used in combination with other keys, provides “hot-key” combinations that access system control functions, such as screen contrast, brightness, volume output, and the BIOS setup utility.
Table 1-4 Hot Key á+↑ Fn+á+↓ Fn+á+→ Fn+á+← Hot Key Descriptions Icon Function Description Brightness Up Increases screen brightness Brightness Down Decreases screen brightness Contrast Up Increases screen contrast (not available for TFT displays) Contrast Down Decreases screen contrast (not available for TFT displays) Fn+↑ Fuel Gauge Up With the fuel gauge displayed, moves the fuel gauge up Fn+↓ Fuel Gauge Down With the fuel gauge displayed, moves the fuel gauge down Fn+→ Fuel Gauge Righ
1.3 System Specification Overview Table 1-6 System Specifications Item Microprocessor Memory System / Main External cache Standard Optional ® Intel Pentium II 266 MHz processor 64MB Dual 64-bit memory banks Expandable to 128MB using 8/16/32/64MB soDIMMs 512KB L2 cache (synchronous SRAM) Flash BIOS 256KB Storage system One 2.5-inch, high-capacity Enhanced-IDE hard disk One high-speed IDE CD-ROM drive module Higher-capacity E-IDE hard disk Second optional hard disk drive module (3-inch) One 3.
Table 1-6 System Specifications Item Standard One fast infrared port (IrDA-compliant) External IR adapter One 3.5mm minijack microphone-in/line-in jack Microphone or line-in device One 3.5mm minijack speaker-out/line-out jack Speakers or headphones One USB port USB device Weight with FDD with CD-ROM (includes battery) 3.5 kg. (7.5 lbs.) 3.8 kg. (7.8 lbs.) Dimensions Round contour Main footprint LxWxH 309x245x56mm 12.2” x 9.6” x 2.
1.
1.4.
1.4.
1.4.
1.4.
1.5 Jumpers and Connectors 1.5.
CN19, CN18 CN16 SW1 CN17 CN20 SW2 ON OFF 1 4 SI2 CN22 SI1 CN20, CN19 CN17 CN20 DC-DC converter connector Left speaker connector Debug port Figure 1-10 Mainboard Jumpers and Connectors (Bottom Side) CN22 CN16 SW1 SW2 Battery connector Right speaker connector Reset Switch Jumper Setting The following table shows the settings of the mainboard’s bottom side jumper pads.
1.5.
1.6 System Configurations and Specifications 1.6.
Table 1-10 I/O Address Map Address Range Device Real-time clock and NMI mask DMA page register Interrupt controller-2 DMA controller-2 Hard disk select Hard disk select CD-ROM select CD-ROM select Audio Audio -default Audio Audio Parallel port 3 COM 4 COM 2 -IrDA MPU-401 port -default MPU-401 port MPU-401 port MPU-401 port Parallel port 2 FM synthesizer Parallel port 1 Video subsystem 070 -071 080 -08F 0A0 -0A1 0C0 -0DF 1F0 -1F7 3F6 -3F7 170 -177 376 -377 220 -22F 240 -24F 260 -26F 280 -28F 278 -27F 2E8
1.6.
Table 1-12 GPIO Port Definition Map I GPIO/Signal Pin # I/O Description GPI1 (DK3_DOCKIRQ#) P19 O 0: Detect Docking IRQ GPI2/REQA# (PX3_OEM0) M1 O OEM detection GPI3/REQB# (SM5_BAYSW) N2 O Detect FDD/CD bay 1: installed, 0: not installed GPI4/REQC# (CF5_FDD/CD#) P3 O Detect FDD or CD installed 1: FDD, 0: CD GPI5/APICREQ# K18 O NC GPI6/IRQ8# (RT3_IRQ8#) Y20 O 0: RTC wake GPI7/SERIRQ (PM3_IRQSER) J19 O Serial IRQ GPI8/THRM# (SM5_OVTMP#) H19 O 0: Enable over temperature of C
Table 1-13 GPIO Port Definition Map II GPIO I/O Description P1.7 (IS5_IRQ12) O IRQ12 P2.0 (KB5_MEMB0A0) I Address 0 of memory bank 0 P2.1 (KB5_MEMB0A1) I Address 1 of memory bank 0 P2.2 (KB5_MODE) I Detect KBD mode (1:US/EC 0:Japan) P2.3 I NC P2.4 (KB5_MEMB1A0) I Address 0 of memory bank 1 P2.5 (KB5_PSWD) I Enable Password P2.6 (KB5_MEMB1A1) I Address 1 of memory bank 1 P2.7 (PX3_OEM0) I Address 1 of memory bank 1 P3.0 (SM5_TXD) I Receiving data from SMC to KBC P3.
Table 1-13 GPIO Port Definition Map II GPIO I/O Description P2.1 O NC P2.2 (SM5_BAYSW) I Detect FDD/CD bay installed or not P2.3 O NC P2.4 O NC P2.5 O NC P2.6 O NC P2.7 O NC P3.0 (SM5_RXD) I Receiving data from KBC to SMC P3.1 (SM5_TXD) O Transmitting data from SMC to KBC P3.2 (SM5_DOCKSW) I Dock switch sense P3.3 (CF5_DOCKED) I Detect completely docked or not P3.4 (SM5_LIDSW) I Lid switch sense P3.5 (SM5_OVTMP#) O CPU or system over temperature P3.6 O NC P3.
Device Device ID Assignment MTXC North Bridge 0 AD11 PIIX4 ISA Bridge 1 AD18 (Function 0) PIIX4 IDE controller 1 AD18 (Function 1) PIIX4 USB controller 1 AD18 (Function 2) PIIX4 PM/SMBUS controller 1 AD18 (Function 3) PCI VGA(NM2160) 2 AD13 PCI Cardbus controller A AD21 PCI Ethernet (Am79C970A) (ACER Dock III) C AD23 PCI CardBus (TI 1131) (ACER Dock V) C AD23 1.6.
1.6.7.1 PMU Timers There are several devices related timers available on the V1-LS chip. Each timer may have zero or more devices assigned to the timer for the purpose of retriggering the timer. Table 1-15 PMU Timers List Item Descriptions Video timer Timer value 30sec, 1min, 1.5min, 2min, 2.5min, 3min, 3.5min, 4min, 4.
Table 1-15 PMU Timers List Item System activities and timer retriggers Descriptions System activities − Power off either or both FDD and CD-ROM. Tri-state FDD and CD-ROM interfaces and stop IDE controller clock. Timer retriggers − The I/O access to 3F2, 3F4, 3F5(FDD), 3F7, 376(CD ROM) will retrigger the timer. Detective hardware change 1.6.7.2 • 1. The PX3_FDDBEN signal on pin-M3 of U21(PIIX4) is from L to H. CD-ROM buffer is disabled. 2.
3. CD-ROM Reset [pin-U13 of U21(PX3_CDRST#) of PIIX4]. The reset pin is used to assert the hard reset needed for the CD-ROM during power up. The reset pin is asserted before CD-ROM power up and is deasserted after CD-ROM power up and before the buffer is enabled. • Floppy The floppy has two components involved in the process. The floppy drive and the controller imbedded in the 87338 super I/O chip. The FDC enable/disabled function is controlled by 87338 chip.
Recovery from power down is the opposite procedure. • SIR (UART) The FIR port is basically UART2. The UART operates off of a 14MHz clock. The IR port has a DA converter. The UART2 disable control circuit is within the 87338 chip. 1. Tri-state the UART2 output pins. 2. Disable the 14MHz clock (If the floppy and the serial port are also disabled). If the 14MHz is disabled through the National power down mode, then all serial and floppy functions will fail.
• CPU The CPU clock. The clock to the CPU can be physically stopped. The chip is static, so the current state is retained. During a clock stop state, the CPU is stopped and the internal cache and external bus signals are inoperative. Therefore, any bus master or DMA activity is halted as well. CPU thermal alarm.
For suspend-to-disk, all devices are read, saved to local memory and the local memory, video memory are saved to a disk file which is created by SLEEP MANAGER utility. The machine is then commanded to an off state. • Resume events for zero-volt suspend(suspend-to-disk) The only resume event for zero-volt suspend is the raising of the lid of the computer. This electronically enables the power to the rest of the machine. • Resume events for static suspend (suspend-to-memory) 1. Resume on schedule.
1.6.9 BIOS Table 1-17 BIOS Specifications Item Specification BIOS programming vendor Acer BIOS version V3.0 BIOS ROM type Intel 28F002, Flash ROM with boot block protection BIOS ROM size 256KB BIOS ROM package type 40-pin TSOP Same BIOS for TFT LCD type Yes Boot from CD-ROM feature Yes Support protocol PCI V2.1, APM V1.1, E-IDE and PnP(ESCD format) V1.0a BIOS flash security protection Provide boot-block protection1 feature.
1.6.10.
1.6.12 Video Display Modes Table 1-21 Video Display Specification Item Specification Chip vendor NeoMagic Chip name NMG2160 Chip voltage 3.3 Volts ZV port support (Y/N) Yes Graph interface (ISA/VESA/PCI) PCI bus Max. resolution (LCD) 800x600 (16M colors) True Color Max. resolution (Ext. CRT) 1024x768 (64K colors) High Color 1.6.12.1 External CRT Resolution Modes Table 1-22 External CRT Resolution Modes Resolution x Color on Ext.
1.6.13 Audio Table 1-24 Audio Specifications Item Specification Chipset Neomagic-3097 Audio onboard or optional Built-in Mono or stereo stereo Resolution 16-bit Compatibility Sound Blaster Game, Windows Sound System, Plug&Play ISA 1.
1.6.15 Parallel Port Table 1-26 Parallel Port Specifications Item Specification Number of parallel ports 1 ECP/EPP support Yes (by BIOS Setup) ECP DMA channel (by BIOS Setup) DRQ1 or DRQ3 Connector type 25-pin D-type Connector location Rear side Selectable parallel port (by BIOS Setup) Parallel 1 (378h, IRQ7) or Parallel 2 (3BCh, IRQ7) or Parallel 3 (278h, IRQ5) or Disabled 1.6.
1.6.18 SIR/FIR Table 1-29 SIR/FIR Specifications Item Vendor & model name Specification IBM(31T1100A) Input power supply voltage 5V Transfer data rate 115.2 Kbit/s(Max)(SIR)~4 Mbit/s(FIR)(Max) Transfer distance 100cm Compatible standard IrDA (Infrared Data Association) Output data signal voltage level Active Non-active 0.5 Vcc-0.
1.6.
1.6.22 Hard Disk Drive Table 1-33 Hard Disk Drive Specifications Item Specification Vendor & Model Name IBM DTCA-23240 IBM DTCA-24090 Drive Format Capacity (GB) 4.09 3.24 Bytes per sector 512 512 Logical heads 16 16 Logical sectors 63 63 Logical cylinders 6304 7944 Physical read/write heads 4 Disks 2 Rotational speed (RPM) 4000 4000 Performance Specifications Buffer size (KB) 512 512 Interface ATA-2 ATA-2 Data transfer rate (disk-buffer, Mbytes/s) 6.47 ~ 10.45 6.
1.6.24 Battery Table 1-35 Battery Specifications Item Specification Vendor & Model Name Sony BTP-S31 Battery Gauge Yes Battery type Li-Ion Cell capacity 2700mAH Cell voltage 3.6V Number of battery cell 6-Cell Package configuration 3 serial, 2 parallel Package voltage 10.8V Package capacity 58.3WH Second battery No 1.6.25 DC-DC Converter DC-DC converter generates multiple DC voltage level for whole system unit use, and offer charge current to battery.
1.6.26 DC-AC Inverter DC-AC inverter is used to generate very high AC voltage, then supply to LCD CCFT backlight use. The DC-AC inverter area should be void to touch while the system unit is turned on. Table 1-37 DC-AC Inverter Specifications Item Specification Vendor & Model Name Ambit T62-055.C.00 Ambit T62-088.C.00 Used LCD type IBM ITSV50D (12.1” TFT) LG LP133X1 (13.3” TFT) Input voltage (V) 7 ~ 19 7 ~ 19 Output voltage (Vrms, with load) 650 (typ.) 650 (typ.
Figure 1-13 System Introduction Charger DC-AC Inverter 68-pin Two CardBus Slots 240-pin Docking Swappable FDD, CD-ROM, removable 3” HDD module DMI 2.0 with Intel LDCM IBM IrDA/FIR 6832 CardBus chip 256KB PMU/System/Video BIOS NS87338 Super I/O controller PCI IDE 9-pin Serial Port 12.1” SVGA TFT, 13.3” XGA TFT 2.5” 12.7mm HDD 3.0GB+ 2MB video memory . . . . . .
1-42 Figure 1-14 SMC 83C552 16 MHz 14.318MHz IDE KeyBoard, Mouse Touch Pad RTC KBC 80C51SL Flash BIOS SIO AUDIO NMA1 USB PIO FDD FIR CRT LCD CARDBUS CTRL PD6832 ZV L2 CACHE 32KX32 HOST BUS MMO MODULE VIDEO CTRL NM2160 440BX SYSTEM CONTROLLER SUPER I/O NS97338 24 MHz 14.318MHz PIIX4 PCI TO EIO BRG IDE,USB, RTC 32.768KHz USB(48MHz) PCICLK(30/33MHz) HCLK(60/66MHz) CD EIO BUS CLOCK GEN. IMICS651 MD[0..63] SDRAM MA[0..
1.8 Environmental Requirements Table 1-39 Environmental Requirements Item Specification Temperature Operating (ºC) +5 ~ +35 Non-operating(ºC)(unpacked) -10 ~ +60 Non-operating(ºC)(storage package) -20 ~ +60 Humidity Operating (non-condensing) 20% ~ 80% Non-operating (non-condensing) (unpacked) 20% ~ 80% Non-operating (non-condensing) (storage package) 20% ~ 90% Operating Vibration (sine mode) Operating 5 -25.6Hz, 0.38mm; 25.6 -250Hz, 0.
1.9 Mechanical Specifications Table 1-40 Mechanical Specifications Item Specification Weight (includes battery and FDD) 12.1 TFT SVGA LCD and 12.5mm HDD Adapter 3.3 kgs (7.2 lbs) 230 g (0.52 lb) Dimensions round contour main footprint 297~313mm x 233~240mm x 50~53mm 11.7” x 9.
& K D S W H U Major Chips Description This chapter discusses the major components. 2.1 Major Component List Table 2-1 Major Chips List Component Vendor Description PIIX4(82371AB) Intel South Bridge NM2160 NeoMagic Flat Panel Video Accelerator NMA1 NeoMagic Audio chip 87C552 Philips Single-chip 8-bit controller for SMC (System Management Controller) NS97338 NS (National Semiconductor) Super I/O controller CL-PD6832 Cirrus Logic PCI-to-CardBus Host Adapter T62.036.C.
2.2 Intel PIIX4 PIIX4 is a multi-function PCI device that integrates many system-level functions. PCI to ISA/EIO Bridge PIIX4 is compatible with the PCI Rev 2.1 specification, as well as the IEEE 996 specification for the ISA (AT) bus. On PCI, PIIX4 operates as a master for various internal modules, such as the USB controller, DMA controller, IDE bus master controller, distributed DMA masters, and on behalf of ISA masters.
The timer/counter block contains three counters that are equivalent in function to those found in one 82C54 programmable interval timer. These three counters are combined to provide the system timer function, refresh request, and speaker tone. The 14.31818-MHz oscillator input provides the clock source for these three counters. PIIX4 provides an ISA-Compatible interrupt controller that incorporates the functionality of two 82C59 interrupt controllers.
Enhanced Power Management PIIX4’s power management functions include enhanced clock control, local and global monitoring support for 14 individual devices, and various low-power (suspend) states, such as Power-On Suspend, Suspend-to-DRAM, and Suspend-to-Disk. A hardware-based thermal management circuit permits software-independent entrance to low-power states. PIIX4 has dedicated pins to monitor various external events (e.g., interfaces to a notebook lid, suspend/resume button, battery low indicators, etc.
• Full Support for Advanced Configuration and Power Interface (ACPI) Revision 1.
The 82371AB PCI ISA IDE Xcelerator (PIIX4) is a multi-function PCI device implementing a PCI-toISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an Enhanced Power Management function. As a PCI-to-ISA bridge, PIIX4 integrates many common I/O functions found in ISA-based PC systems—two 82C37 DMA Controllers, two 82C59 Interrupt Controllers, an 82C54 Timer/Counter, and a Real Time Clock. In addition to compatible transfers, each DMA channel supports Type F transfers.
2.2.
2.2.4 Pin Descriptions This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present after the signal name, the signal is asserted when at the high voltage level. The terms assertion and negation are used exclusively.
Table 2-2 82371AB Pin Descriptions Name Type Description PCI BUS INTERFACE AD[31:0] I/O PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical byte address (32 bits). During subsequent clocks, AD[31:0] contain data. A PIIX4 Bus transaction consists of an address phase followed by one or more data phases. Little-endian byte ordering is used.
Table 2-2 Name IRDY# 82371AB Pin Descriptions Type I/O Description INITIATOR READY. IRDY# indicates PIIX4’s ability, as an Initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates PIIX4 has valid data present on AD[31:0]. During a read, it indicates PIIX4 is prepared to latch data.
Table 2-2 82371AB Pin Descriptions Name TRDY# Type I/O Description TARGET READY. TRDY# indicates PIIX4’s ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that PIIX4, as a Target, has place valid data on AD[31:0]. During a write, it indicates PIIX4, as a Target is prepared to latch data.
Table 2-2 Name IOW# 82371AB Pin Descriptions Type I/O Description I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave may latch data from the ISA data bus (SD[15:0]). IOW# is an output when PIIX4 owns the ISA Bus. IOW# is an input when an external ISA master owns the ISA Bus. During Reset: High-Z After Reset: High During POS: High LA[23:17]/ I/O GPO[7:1] ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory on the ISA Bus up to 16 Mbytes.
Table 2-2 Name SA[19:0] 82371AB Pin Descriptions Type I/O Description SYSTEM ADDRESS[19:0]. These bi-directional address lines define the selection with the granularity of 1 byte within the 1-Megabyte section of memory defined by the LA[23:17] address lines. The address lines SA[19:17] that are coincident with LA[19:17] are defined to have the same values as LA[19:17] for all memory cycles. For I/O accesses, only SA[15:0] are used, and SA[19:16] are undefined.
Table 2-2 Name KBCCS#/ 82371AB Pin Descriptions Type O GPO26 Description KEYBOARD CONTROLLER CHIP SELECT. KBCCS# is asserted during I/O read or write accesses to KBC locations 60h and 64h. It is driven combinatorially from the ISA addresses SA[19:0] and LA[23:17]. If the keyboard controller does not require a separate chip select, this signal can be programmed to a general purpose output. During Reset: High After Reset: High During POS: High/GPO MCCS# O MICROCONTROLLER CHIP SELECT.
Table 2-2 Name XOE#/ 82371AB Pin Descriptions Type O GPO23 Description X-BUS TRANSCEIVER OUTPUT ENABLE. XOE# is tied directly to the output enable of a 74’245 that buffers the X-Bus data, XD[7:0], from the system data bus, SD[7:0]. XOE# is asserted anytime a PIIX4 supported X-Bus device is decoded, and the devices decode is enabled in the X-Bus Chip Select Enable Register (BIOSCS#, KBCCS#, RTCCS#, MCCS#) or the Device Resource B (PCCS0#) and Device Resource C (PCCS1#).
Table 2-2 Name 82371AB Pin Descriptions Type Description INTERRUPT CONTROLLER/APIC SIGNALS APICACK#/ O GPO12 APIC ACKNOWLEDGE. This active low output signal is asserted by PIIX4 after its internal buffers are flushed in response to the APICREQ# signal. When the I/O APIC samples this signal asserted it knows that PIIX4’s buffers are flushed and that it can proceed to send the APIC interrupt. The APICACK# output is synchronous to PCICLK.
Table 2-2 Name 82371AB Pin Descriptions Type Description IRQ 12/M I INTERRUPT REQUEST 12. In addition to providing the standard interrupt function as described in the pin description for IRQ[3:7,9:11,14:15], this pin can also be programmed to provide the mouse interrupt function. When the mouse interrupt function is selected, a low to high transition on this signal is latched by PIIX4 and an INTR is generated to the CPU as IRQ12.
Table 2-2 Name INIT 82371AB Pin Descriptions Type OD Description INITIALIZATION. INIT is asserted in response to any one of the following conditions. When the System Reset bit in the Reset Control Register is reset to 0 and the Reset CPU bit toggles from 0 to 1, PIIX4 initiates a soft reset by asserting INIT. PIIX4 also asserts INIT if a Shut Down Special cycle is decoded on the PCI Bus, if the RCIN# signal is asserted, or if a write occurs to Port 92h, bit 0.
Table 2-2 Name 82371AB Pin Descriptions Type Description PCICLK I FREE-RUNNING PCI CLOCK. A clock signal running at 30 or 33 MHz, PCICLK provides timing for all transactions on the PCI Bus. All other PCI signals are sampled on the rising edge of PCICLK, and all timing parameters are defined with respect to this edge. Because many of the circuits in PIIX4 run off the PCI clock, this signal MUST be kept active, even if the PCI bus clock is not active. OSC I 14.31818-MHZ CLOCK.
Table 2-2 Name PDDACK# 82371AB Pin Descriptions Type O Description PRIMARY DMA ACKNOWLEDGE. This signal directly drives the IDE device DMACK# signal. It is asserted by PIIX4 to indicate to IDE DMA slave devices that a given data transfer cycle (assertion of PDIOR# or PDIOW#) is a DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function. It is not associated with any AT compatible DMA channel.
Table 2-2 Name SDA[2:0] 82371AB Pin Descriptions Type O Description SECONDARY DISK ADDRESS[2:0]. These signals indicate which byte in either the ATA command block or control block is being addressed. If the IDE signals are configured for Primary and Secondary, these signals are connected to the corresponding signals on the Secondary IDE connector. If the IDE signals are configured for Primary Master and Primary Slave, these signals are used for the Primary Slave connector.
Table 2-2 Name SDIOR# 82371AB Pin Descriptions Type O Description SECONDARY DISK IO READ. In normal IDE mode, this is the command to the IDE device that it may drive data onto the SDD[15:0] lines. Data is latched by the PIIX4 on the negation edge of SDIOR#. The IDE device is selected either by the ATA register file chip selects (SDCS1#, SDCS3#) and the SDA[2:0] lines, or the IDE DMA slave arbitration signals (SDDACK#).
Table 2-2 Name 82371AB Pin Descriptions Type Description POWER MANAGEMENT SIGNALS BATLOW#/ I BATTERY LOW. Indicates that battery power is low. PIIX4 can be programmed to prevent a resume operation when the BATLOW# signal is asserted. If the Battery Low function is not needed, this pin can be used as a general-purpose input. O CPU CLOCK STOP. Active low control signal to the clock generator used to disable the CPU clock outputs.
Table 2-2 Name SUSA# 82371AB Pin Descriptions Type O Description SUSPEND PLANE A CONTROL. Control signal asserted during power management suspend states. SUSA# is primarily used to control the primary power plane. This signal is asserted during POS, STR, and STD suspend states. During Reset: Low After Reset: High During POS: Low SUSB#/ O GPO15 SUSPEND PLANE B CONTROL. Control signal asserted during power management suspend states. SUSB# is primarily used to control the secondary power plane.
Table 2-2 82371AB Pin Descriptions Name Type GPO[30:0] O Description GENERAL PURPOSE OUTPUTS. These output signals can be controlled via the GPIREG register located in Function 3 (Power Management) System IO Space at address PMBase+34h. If a GPO pin is not multiplexed with another signal or defaults to GPO, then its state after reset is the reset condition of the GPOREG register. If the GPO defaults to another signal, then it defaults to that signal’s state after reset.
Signal Name Multiplexed With Default Control Register and Bit (PCI Function 1) Notes GPO[9:11] GNT[A:C]# GPO GENCFG Bits [8:10] Not available as GPO if using for PC/PCI. Can be individually enabled, so GPO[11] is available if REQ[C]# not used. GPO12 APICACK# GPO XBCS Bit 8 Not available as GPO if using external APIC. GPO13 APICCS# GPO XBCS Bit 8 Not available as GPO if using external APIC. GPO14 IRQ0 GPO XBCS Bit 8 Not available as GPO if using external APIC.
Table 2-2 Name 82371AB Pin Descriptions (continued) Type Description CONFIG2 I CONFIGURATION SELECT 2. This input signal is used to select the positive or subtractive decode of FFFF0000h–FFFFFFFFh memory address range (top 64 Kbytes). If CONFIG[2]=0, the PIIX4 will positively decode this range. If CONFIG[2]=1, the PIIX4 will decode this range with subtractive decode timings only. The input value of this pin must be static and may not dynamically change during system operations. PWROK I POWER OK.
2.3 NM2160 The NM2160 is a high performance Flat Panel Video Accelerator that integrates in one single chip, 2 Mbytes of High Speed DRAM, 24-bit true-color RAMDAC, Graphics/Video Accelerator, Dual clock synthesizer, TV Out support, ZV(Zoomed Video) port, Z-Buffer Data Stripping, PCI Bus Mastering and a high speed glueless 32-bit PCI 2.1 compliance interface.
• High Speed 2Mbytes of integrated DRAM • 128 bit Memory Interface • Bus Support • PCI 2.1 compliance Local Bus(Zero wait states) • 3.
2.3.
2.3.
Table 2-3 NM2160 Pin Descriptions Number Pin name I/O Description 72 FRAME# I/O Frame This active-low signal is driven by the bus master to indicate the beginning and duration of an access.
Table 2-3 NM2160 Pin Descriptions Number Pin name I/O Description 83 XCKEN I External Clock Enable This pin is used to select between internally synthesized clocks or externally supplied clocks. A low level on the pin selects internal mode and a high level selects external mode. In the external clock mode, the internal clock synthesizers will be disabled completely. Both PVCLK and PMCLK pins should be driven with the desired clock rates in external mode.
Table 2-3 Number NM2160 Pin Descriptions Pin name I/O Description 108 FPBACK O Flat Panel Backlight This is used to control the backlight power to the panels or as a General Purpose Output Pin as defined by register CR2F bits 3&2 7 6 5 4 3 2 176 174 172 171 170 169 18 17 16 15 14 13 117 PDATA35 PDATA34 PDATA33 PDATA32 PDATA31 PDATA30 PDATA29 PDATA28 PDATA27 PDATA26 PDATA25 PDATA24 PDATA23 PDATA22 PDATA21 PDATA20 PDATA19 PDATA18 PDATA17/ LCD_ID0 PDATA16/ LCD_ID1 PDATA15/ LCD_ID2 PDATA14/ LCD_ID3 PDA
Table 2-3 Number NM2160 Pin Descriptions Pin name I/O Description 96 B O (Analog) BLUE This DAC analog output drives the CRT interface 101 REXT I (Analog) DAC Current reference This pin is used as a current reference by the internal DAC.
Table 2-3 Number NM2160 Pin Descriptions Pin name I/O Description 167 166 165 164 163 162 161 160 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 I Chrominance Data 7:0 These are the 8-bits of chrominance data that are input to the ZV port of NM2160 159 158 155 152 151 150 149 148 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 I Luminance Data 7:0 These are the 8-bits of luminance data that are input to the ZV port of NM2160 144 HREF I Horizontal Synchronization Pulse: This input signal provides the horizontal synchronization puls
Table 2-3 Number NM2160 Pin Descriptions Pin name I/O Description 136, 154, 173 DVSS 105 AVSSM Analog ground for MCLK synthesizer 104 AVSSV Analog ground for VCLK synthesizer 99 AVSSR1 Analog ground for DAC 100 AVSSR2 Analog ground for DAC current reference 91 AVSSX1 Analog ground for crystal oscillator 25, 42, 57, 78 HVDD Host bus interface VDD.
2.4 NMA1 NMA1 is a single audio chip that integrates OPL3 FM and its DAC, 16bit Sigma-delta CODEC, MPU401 MIDI interface, and a 3D enhanced controller including all the analog components which is suitable for multi-media application. This LSI is fully compliant with Plug and Play ISA 1.0a, and supports all the necessary features, i.e. 16bit address decode, more IRQs and DMAs in compliance with PC’96. This LSI also supports the expandability, i.e.
2.4.
2.4.
2.4.
Table 2-4 NMA1 Pin Descriptions Pin name Number ADFLTR 1 VOCOL 1 I/O Description Right input filter O Left voice output VOCOR 1 O Right voice output VOCIL 1 I Left voice input VOCIR 1 I Right voice input Miscellaneous pins: 14 pins SYEN 1 I External synthesizer enable input SYCS 1 O External synthesizer chip select output SYCLK 1 I External synthesizer clock input or ZV clock input SYLR 1 I External synthesizer L/R clock input or ZV L/R clock input SYIN 1 I Externa
2.5 Philips 87C552 System Management Controller The 87C552 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 87C552 has the same instruction set as the 80C51.
2.5.
Pin Diagram 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 P4.2/CMSR2 P4.1/CMSR1 P4.0/CMSR0 EW# PWM1# PWM0# STADC VDD P5.0/ADC0 P5.1/ADC1 P5.2/ADC2 P5.3/ADC3 P5.4/ADC4 P5.5/ADC5 P5.6/ADC6 P5.7/ADC7 AVDD 2.5.3 P4.3/CMSR3 P4.4/CMSR4 P4.5/CMSR5 P4.6/CMT0 P4.7/CMT1 RST P1.0/CT0I P1.1/CT1I P1.2/CT2I P1.3/CT3I P1.4/T2 P1.5/RT2 P1.6/SCL P1.7/SDA P3.0/RxD P3.1/TxD P3.2/INT0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 AVSS AVref+ AVref– P0.0/AD0 P0.
2.5.4 Pin Descriptions Table 2-5 Mnemonic 87C552 Pin Descriptions Pin No. Type Name And Function VDD 2 I Digital Power Supply: +5V power supply pin during normal operation, idle and power-down mode. STADC 3 I Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be started by software). PWM0# 4 O Pulse Width Modulation: Output 0.
Table 2-5 Mnemonic P4.0-P4.7 P5.0-P5.7 87C552 Pin Descriptions Pin No. Type 7-14 I/O Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include: 7-12 O CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with timer T2. 13, 14 13, 14 O CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2. 68-62, I Port 5: 8-bit input port. 1 Name And Function ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC.
2.6 NS97338VJG Super I/O Controller The PC97338VJG is a single chip solution for most commonly used I/O peripherals in ISA, and EISA based computers. It incorporates a Floppy Disk Controller(FDC), two full featured UARTs, and an IEEE 1284 compatible parallel port Standard PC-AT address decoding for all the peripherals and a set of configuration registers are also implemented in this highly integrated member of the Super l/O family.
• The Bidirectional Parallel Port: • Enhanced Parallel Port(EPP) compatible • Extended Capabilities Port(ECP) compatible, including level 2 support • Bidirectional under either software or hardware control • Compatible with ISA, and EISA, architectures • Ability to multiplex FDC signals on parallel port pins allows use of an external Floppy Disk Drive(FDD) • Includes protection circuit to prevent damage to the parallel port when a connected printer is powered up or is operated at a higher voltage • The U
2.6.2 Block Diagram Config.
2.6.
2.6.4 Pin Description Table 2-6 Pin NS97338VJG Pin Descriptions No. I/O Description A15-A0 67, 64, 62-60, 29, 1928 I Address. These address lines from the microprocessor determine which internal register is accessed. A0-A15 are don't cares during DMA transfer. /ACK 83 I Parallel Port Acknowledge. This input is pulsed low by the printer to indicate that it has received the data from the parallel port. This pin has a nominal 25 KΩ pull-up resistor attached to it.
Table 2-6 Pin /CTS1, /CTS2 NS97338VJG Pin Descriptions No. 72, 64 I/O I Description UARTs Clear to Send. When low, this indicates that the modem or data set is ready to exchange data. The /CTS signal is a modem status input. The CPU tests the condition of this /CTS signal by reading bit 4 (CTS) of the Modem Status Register (MSR) for the appropriate serial channel. Bit 4 is the complement of the CTS signal. Bit 0 (DCTS) has no effect on the transmitter. /CTS2 is multiplexed with A13.
Table 2-6 Pin NS97338VJG Pin Descriptions No. I/O Description /DR1 (PPM Mode) 83 O FDC Drive Select 1. This pin offers an additional Drive Select signal in PPM Mode when PNF = 0. It is drive select 1 when bit 4 of FCR is 0. It is drive select 0 when bit 4 of FCR is 1. This signal is active low. /DR23 47 O FDC Drive 2 or 3. /DR23 is asserted when either Drive 2 or Drive 3 is assessed(except during logical drive exchange). /DRATE0 /DRATE1 (Normal Mode) 50, 49 O FDC Data Rate 0, 1.
Table 2-6 Pin NS97338VJG Pin Descriptions No. I/O Description /HDSEL (Normal Mode) 32 O FDC Head Select. This output determines which side of the FDD is accessed. Active selects side 1, inactive selects side 0. /HDSEL (PPM Mode) 77 O FDC Head Select. This pin offers an additional Head Select signal in PPM Mode when PNF = 0. IDLE 41 O FDD IDLE. IDLE indicates that the FDC is in the IDLE state and can be powered down.
Table 2-6 Pin NS97338VJG Pin Descriptions No. I/O Description IRTX 63 O MR 100 I Master Reset. Active high output that resets the controller to the idle state and resets all disk interface outputs to their inactive states. The DOR, DSR, CCR, Mode command, Configure command, and Lock command parameters are cleared to their default values. The Specify command parameters are not affected /MSEN0 /MSEN1 (Normal Mode) 50, 49 I Media Sense.
Table 2-6 NS97338VJG Pin Descriptions Pin /RI1 /RI2 No. 68, 60 I/O I Description UARTs Ring Indicator. When low, this indicates that a telephone ring signal has been received by the modem. The /RI signal is a modem status input whose condition is tested by the CPU by reading bit 6 (RI) of the Modem Status Register (MSR) for the appropriate serial channel. Bit 6 is the complement of the RI signal.
Table 2-6 NS97338VJG Pin Descriptions Pin No. I/O /TRK0 (PPM Mode) 91 VDDB, C 48, 97 Power Supply. This is the 3.3V/5V supply voltage for the PC87332VJG circuitry. VSSB-E 40, 7, 88, 59 Ground. This is the ground for the PC87332VJG circuitry. /WAIT 82 I EPP Wait. This signal is used in EPP mode by the parallel port device to extend its access cycle. It is an active low signal. /WDATA (Normal Mode) 37 O FDC Write Data.
2.7 CL-PD6832: PCI-to-CardBus Host Adapter The CL-PD6832 is a single-chip PC Card host adapter solution capable of controlling two fully independent CardBus sockets. The chip is compliant with PC Card Standard, PCMCIA 2.1, and JEDIA 4.1 and is optimized for use in notebook and handheld computers where reduced form factor and low power consumption are critical design objectives. The CL-PD6832 chip employs energy-efficient, mixed-voltage technology that can reduce system power consumption.
• 208-pin PQFP 2.7.2 Pin Diagram Figure 2-10 2.7.3 CL-PD6832 Pin Diagram Pin Descriptions The following conventions apply to the pin description tables: • A pound sign (#) at the end of a pin name indicates an active-low signal for the PCI bus. • A dash (-) at the beginning of a pin name indicates an active-low signal for the PCMCIA bus.
• • • An asterisk (*) at the end of a pin name indicates an active-low signal that is a general-interface for the CL-PD6832. A double-dagger superscript (º) at the end of the pin name indicates signals that are used for power-on configuration switches. The l/O-type code (I/O) column indicates the input and output configurations of the pins on the CL-PD6832.The possible types are defined below.
The following table lists the pin descriptions Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin Number I/O Power PCI Bus Interface Pins AD[31:0] PCI Bus Address Input / Data Input/Outputs: These pins connect to PCI bus signals AD[31:0]. 4-5, 7-12, 16-20, 22-24, 38-43, 4546, 48 49, 51-56 I/O C/BE[3:0]# PCI Bus Command / Byte Enables: The command signaling and byte enables are multiplexed on the same pins.
Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin Number I/O Power SERR# System Error: This output is pulsed by the CLPD6832 to indicate an address parity error. 34 OOD 4 PAR Parity: This pin is sampled the clock cycle after completion of each corresponding address or write data phase. For read operations this pin is driven from the cycle after TRDY# is asserted until the cycle after completion of each data phase. It ensures even parity across AD[31:0] and C/BE[3:0]#.
Table 2-7 Pin Name CL-PD6832 Pin Descriptions Description Pin Number I/O Power SIN# /INTD# /ISDAT Serial Interrupt Input / PCI Bus Interrupt D / Serial IRQ Data: In PCI Interrupt Signaling mode, this output can be used as an interrupt output connected to the PCI bus INTD# interrupt line. In PC/PCI Serial Interrupt Signaling mode, this pin is the serial interrupt input, SIN#.
Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin No. (socket A) Pin No. (socket B) I/O Power Socket Interface Pins -REG/ CC/BE3# Register Access: In Memory Card Interface mode, this output chooses between attribute and common memory. In l/O Card Interface mode, this signal is active (low) for non DMA transfers and high for DMA transfers. In ATA mode this signal is always high. In CardBus mode, this pin is the command and byte enables.
Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin No. (socket A) Pin No. (socket B) I/O Power A12/ CC/BE2# PCMCIA socket address 12 output. In CardBus mode, this pin is the Cardbus C/BE2# signal. 97 173 I/O 2 or 3 A[11:9]/ CAD[12,9,14] PCMCIA socket address 11:9 outputs. In CardBus mode, these pins are the Cardbus address/data bits 12, 9, and 14, respectively. 77, 73, 80 153, 149, 155 I/O 2 or 3 A8/ CC/BE1# PCMCIA socket address 8 output.
Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin No. (socket A) Pin No. (socket B) I/O Power -IORD/ CAD13 I/O Read: This output goes active (low) for l/O reads from the socket to the CLPD6832. In CardBus mode, this pin is the CardBus address/data bit 13. 78 154 I/O 2 or 3 -IOWR/ CAD15 I/O Write: This output goes active (low) for l/O writes from the CL-PD6832 to the socket. In CardBus mode, this pin is the CardBus address/data bit 15.
Table 2-7 Pin Name CL-PD6832 Pin Descriptions Description Pin No. (socket A) Pin No. (socket B) I/O Power -CE2/ CAD10 Card Enable pin is driven low by the CLPD6832 during card access cycles to control byte/word card access. -CE1 enables even-numbered address bytes, and -CE2 enables odd-numbered address bytes. When configured for 8-bit cards, only -CE1 is active and A0 is used to indicate access of odd- or even-numbered bytes.
Table 2-7 CL-PD6832 Pin Descriptions Pin Name Description Pin No. (socket A) Pin No. (socket B) I/O Power BVD1/ -STSCHG/ -RI/ -CSTSCHG Battery Voltage Detect 1 / Status Change / Ring Indicate: In Memory Card Interface mode, this input serves as the BVD1 (battery-dead status) input. In I/O Card Interface mode, this input is the -STSCHG input, which indicates to the CL-PD6832 that the card's internal status has changed.
Table 2-7 Pin Name CL-PD6832 Pin Descriptions Description Pin Number I/O Power Power Control and General Interface Pins SPKR_OUTt Speaker Output: This output can be used as a digital output to a speaker to allow a system to support PCMCIA card fax/modem/voice and audio sound output. This output is enabled by setting the socket’s Misc Control 1 register bit 4 to ‘1’(for the socket whose speaker signal is to be directed from BVD2/-SPKR/-LED to this pin).
Table 2-7 CL-PD6832 Pin Descriptions Pin Name SLATCH/ SMBLCKt Description Serial Latch / System Management Bus Clock: This pin serves as output pin SLATCH when used with the serial interface of Texas Instruments' TPS2202AIDF socket power control chip, and serves as a bidirectional pin SMBCLK when used with Intel's System Management Bus used by Maxim's socket power control chip. This pin is open drain in the SMB mode of operation. In this mode an external pull up is required.
2.8 Ambit T62.036.C DC-DC Converter This T62.036.C DC-DC converter supplies multiple DC(5V, 3,3V, 12V) output to system, and also supplies the battery charge current (0~3.5A). The total inputs from the notebook would be limited by the total output of 65 watts maximum. 2.8.1 Pin Diagram T62.036.C CN1 VDCF - 1 VDCF - 3 GND - 5 DCIN - 7 DCIN - 9 CHARGCL - 11 CHARGFB - 13 GND - 15 CHARGOUT - 17 CHARGOUT - 19 Figure 2-11 2.8.
Table 2-8 T62.036.C Pin Descriptions Pin Name Pin Type Pin No. Description source such as docking station power supply. This level is 2 Amps per volt nominal. The source impedance is less than 1KΩ. CHARGSP I 14 Analog input from the system board to limit the total current consumed by the system from the AC adapter. This signal shall be compared by the module with the CHARGFB from the system mother board and the battery charger output current adjusted until CHARGFB does not exceed CHARGSP.
2.9 Ambit DC-AC Inverter This notebook uses two kinds of DC-AC inverters: One (T62.088.C) is designed for the 13.3-inch TFT (LG LP133X1) LCD, the other (T62.055.C) for the 12.1-inch TFT (IBM ITSV50D) LCD. 2.9.1 T62.055C 2.9.1.1 Pin Diagram T62.055.C CN1 Figure 2-12 2.9.1.2 21 20 1 2 CN3 CN2 3 2 1 T62.055.C Pin Diagram Pin Descriptions Table 2-9 T62.055.C Pin Descriptions Pin Name Pin Type Pin No.
Table 2-9 T62.055.C Pin Descriptions Pin Name Pin Type Pin No. Descriptions BATTLED O 13 This signal is an open collector sink signal to drive LED2. The LED current is limited by a series resistor of 1KΩ. BMCVCC O 14 This a 5 volt supply for powering the LEDs. It should not be used for any other purpose. ADVDD O 18 This is a 5 volt power line for the analog circuits and display LEDs on the inverter board. AUDGND GND 19, 20 This is the return ground for the microphone circuit.
Table 2-10 T62.088.C Pin Descriptions Pin Name ADVDD Pin Type I Pin No. 1 Descriptions This is a 5-volt power line for the analog circuits and display LEDs on the inverter board. MIC_OUT O 2 Microphone preamplifier circuit output AUDGND I/O 3 Microphone circuit return ground GND I/O 4, 5 System ground SGND I/O 6 Signal ground CNTADJ 7 NC BRTADJ I 8 Lamp current control pin (0~3V) PANEL_ON I 9 On/Off (On:1.8V(min), Off:0.
& K D S W H U BIOS Setup Information The computer BIOS setup utility allows you to configure the computer and its hardware settings. The computer comes correctly configured, and you do not need to run the BIOS setup utility to use the computer. However, you might need to use the BIOS utility if you want to customize the way your computer works, or if you receive an error message after making hardware or software changes.
3.1 About My Computer Selecting About My Computer presents you with two screens of details about the computer and its peripherals. These screens are for information only; you cannot change the settings on these screens. The following table tells you what each of the items on the About My Computer screens are.
3.2 System Configuration Selecting System Configuration presents a Basic System Configuration screen, where you can change several items in your computer’s configuration. Press ↑ or ↓ to move from one item to another, and ← or → to change settings. Press F1 to get help on a selected item. Press Esc to exit the Basic System Configuration screen and return to the main BIOS Utility screen. 3.2.1 Date and Time The current date is in “Day-of-the-week Month Day, Year” format—for example, [Mon Aug 11, 1997].
3.2.6 Internal Speaker This parameter lets you enable or disable the internal speaker. The default setting is Enabled. Tip: You can also toggle the speaker on and off by pressing the speaker hot key combination Fn+F7. 3.2.7 Silent Boot When set to Enabled, the computer shows the computer logo onscreen and hides the POST routine messages. The default setting is Enabled. 3.2.8 Fast Boot When set to Enabled, the computer bypasses the memory tests to speed up the boot-up process.
3.3 Advanced System Configuration For advanced users, the System Configuration menu item contains two hidden pages that allow you to view and configure more technical aspects of the computer. Caution: The computer is already tuned for optimum performance and you should not need to access these advanced screens. If you do not fully understand the items in these special screens, do not change their values.
• Hard Disk 32 Bit Access. This parameter allows your hard disk to use 32-bit access. The available values are: Auto and Disabled. The default setting is Auto. Tip: We suggest you set all of these parameters to Auto whenever that choice is available. This allows the computer to use the hard drive at the highest possible performance level. 3.3.4 Onboard Communication Ports The Onboard Communication Ports section allows you to set addresses and interrupts for the computer’s serial and parallel ports.
3.4 Power Saving Options Selecting Power Saving Options on the BIOS Utility main screen presents a screen that allows you to adjust several power-saving settings. 3.4.1 When Lid is Closed The computer’s lid switch acts as its power switch: opening the display wakes up the computer, closing the display puts it to sleep. The When Lid is Closed setting determines which suspend mode the computer enters when the display is closed: Suspend to Disk or Suspend to Memory. The default is Suspend to Disk.
3.4.5 Resume On Schedule When this parameter is set to Enabled, the computer resumes from suspend-to-memory mode at the specified date and time. Enabling this option overrides the suspend-to-disk function. The Resume Date and Resume Time parameters let you set the date and time for the resume operation. The date and time fields take the same format as the System Date and Time parameters in the System Configuration screen.
3.5 System Security When you select System Security from the BIOS Utility main screen, a screen appears that allows you to set security options. Important! If a password is currently present, the system prompts you to input the password before entering the System Security screen. 3.5.1 Supervisor and User Passwords The supervisor and user passwords both prevent unauthorized access to the computer.
3.5.2 Diskette Drive Access Control This parameter allows you to control the read and write functions of the floppy drive. The available options. are: Normal, Write Protect, and Disabled. The default is Normal. With this parameter set to Normal, the floppy drive functions normally. When the parameter is set to Write Protect, all write functions to the floppy drive are disabled, but you can still read from a disk in the floppy drive. When the parameter is set to Disabled, the floppy drive is disabled. 3.
3.6 Reset To Default Settings When you select the Reset To Default Settings from the BIOS Utility main screen, a dialog box appears asking you to confirm that you want to reset all settings to their factory defaults.
& K D S W H U Disassembly and Unit Replacement This chapter contains step-by-step procedures on how to disassemble the notebook computer for maintenance and troubleshooting. To disassemble the computer, you need the following tools: • Wrist grounding strap and conductive mat for preventing electrostatic discharge • Flat-bladed screwdriver • Phillips screwdriver • Hexagonal screwdriver • Tweezers • Plastic stick The screws for the different components vary in size.
a b c Figure 4-1 Removing the Battery Pack Removing all power sources from the system prevents accidental short circuit during the disassembly process.
4.1.2 Connector Types There are two kinds of connectors on the main board: • Connectors with no locks Unplug the cable by simply pulling out the cable from the connector. • Connectors with locks You can use a plastic stick to lock and unlock connectors with locks. The cables used here are special FPC (flexible printed-circuit) cables, which are more delicate than normal plastic-enclosed cables. Therefore, to prevent damage, make sure that you unlock the connectors before pulling out the cables.
Connectors mentioned in the following procedures are assumed to be no-lock connectors unless specified otherwise. 4.1.3 Disassembly Sequence The disassembly procedure described in this manual is divided into eight major sections: • Section 4.2: Removing the module • Section 4.3: Replacing the hard disk drive • Section 4.4: Replacing memory • Section 4.5: Removing the keyboard • Section 4.6: Replacing the CPU • Section 4.7: Removing the display • Section 4.
The following diagram details the disassembly flow.
4.2 Removing the Module If you are going to disassemble the unit, it is advisable to remove the module first before proceeding. Follow these steps to remove the module: 1. Slide out and hold the module release button. 2. Press the module release latch and slide out the module.
4.3 Replacing the Hard Disk Drive Follow these steps: 1. Turn the computer over to access the base. 2. Remove the two screws from the hard disk drive bay cover and remove the cover. Figure 4-5 3. Removing the Hard Disk Drive Bay Cover Lift up (1), then pull out the hard disk drive; then flip the hard disk drive over and unplug the hard disk drive connector. Figure 4-6 Removing the Hard Disk Drive If you want to install a new hard disk drive, reverse the steps described above.
4.4 Replacing Memory The memory slots (SIMM1 and SIMM2) are accessible via the memory door at the base of the unit. Follow these steps to install memory module(s): 1. Turn the computer over to access the base. 2. Remove the screws from the memory door and remove the door. Figure 4-7 Installing a Memory Module 3. Remove the memory module(s) from its shipping container. 4. Align the connector edge of the memory module with the key in the connector.
You must run the Sleep Manager utility after installing additional memory in order for the 0V Suspend function to operate in your system. If Sleep Manager is active, it will auto-adjust the partition/file on your notebook for 0V Suspend to function properly. If you are using an operating system other than Windows 95 or DOS, you may need to re-partition your hard disk drive to allow for the additional memory. Check with your system administrator. 5.
4.5 Removing the Keyboard Follow these steps to remove the keyboard: 1. Slide out the two display hinge covers on both sides of the notebook. Figure 4-9 2. Pull out (first from the edges) and remove the center hinge cover.
3. Lifting out the keyboard takes three steps — (a) lifting up the keyboard, (b) rotating the keyboard to one side, and (c) pulling out the keyboard in the opposite direction. Figure 4-11 4. Lifting Out the Keyboard Flip the keyboard over and unplug the keyboard connectors (CN4, CN5) to remove the keyboard. At this point, you can also remove the touchpad cable from its connector (CN6).
4.6 Replacing the CPU Follow these steps to remove the CPU module. 1. Remove six screws that secure the CPU heat sink to the chassis. Figure 4-13 2. Removing the CPU Heat Sink Remove one screw and pull up the CPU module. (CN8, CN12) When inserting a CPU module, take note of the female and male connectors on the CPU module. These should match the corresponding male and female connectors on the main board.
4.7 Removing the Display Follow these steps to remove the display module. 1. Remove the two screws that secure the display cable to the motherboard. Then unplug the display cable (CN6). CN6 Figure 4-15 2. Unplugging the Display Cable Remove the four display hinge screws. Detach the display from the main unit and set aside.
4.8 Disassembling the Housing This section discusses how to disassemble the housing, and during its course, includes removing and replacing of certain major components like the hard disk drive, memory and the main board. 4.8.1 Detaching the Lower Housing from the Inside Assembly To detach the lower housing from the inside assembly, turn the unit over and remove seven (7) base screws. Then snap out the lower part of the housing.
4.8.2 Detaching the Upper Housing from the Inside Assembly Follow these steps: 1. Remove three screws in the battery bay. Figure 4-18 2. Removing the Battery Bay Screws Turn the unit back over and remove two screws close to the back part of the unit. Then snap out the upper part of the housing — (1) first from the rear of the unit, then (2) the front end of the unit.
4.8.3 Removing the Touchpad Follow these steps to remove the touchpad: 1. Unplug the touchpad connector (CN5). 2. Pull up and remove the touchpad. Figure 4-20 4.8.4 Removing the Touchpad Removing the Main Board Follow these steps to remove the main board from the inside assembly. 1. Unplug the speaker connectors (CN17 and CN23), and the battery pack connector (CN21).
2. Remove four screws to remove the main board from the inside assembly. Figure 4-22 3. Removing the Main Board Remove the charger board (CN19 and CN20) and the multimedia board (CN10 and CN7) from the main board.
4. The PC card slot module is usually part of the main board spare part. This removal procedure is for reference only. To remove the PC card slot module, remove two screws.
4.9 Disassembling the Display Follow these steps to disassemble the display: 1. Remove the teardrop-shaped LCD bumpers at the top of the display and the long bumper on the LCD hinge. Figure 4-25 2. Removing the LCD Bumpers Remove four screws on the display bezel. oor r oor r s s o r s Screw list: M2L6 x2 (for 11.3” or 11.8” LCD) M2.5L6 x2 (for 12.1” LCD) M2.
3. Pull out and remove the display bezel by pulling on the inside of the bezel sides. Figure 4-27 4. Removing the Display Bezel Remove the four display panel screws, and unplug the inverter and display panel connectors. Then tilt up and remove the display panel. s s s s Screw list: sM2.
5. Remove the two display assembly screws and unplug the display cable connector from the display cable assembly. Then remove the LCD inverter and ID boards. Screw list: sM2.
$ S S H Q G $ S S H Q G L [ $ L [ $ Model Number Definition This appendix shows the model number definition of the notebook.
0: 3: w/o HDD, FDD, CD-ROM 3.0GB HDD + FDD + CD-ROM 2: 4: 2.0GB HDD + FDD + CD-ROM 4.0GB HDD + FDD + CD-ROM VU: LCD size T: A-2 12.1” TFT LCD TE: 13.
$ S S H Q G $ S S H Q G L [ % L [ % Exploded View Diagram This appendix includes exploded view diagrams of the notebook. Table B-1 Exploded View Diagram List No. Description B-1 System assembly B-2 13.
$ S S H Q G $ S S H Q G L [ & L [ & Spare Parts List This appendix lists the spare parts of the notebook computer. Table C-1 Spare Parts List Level Description Acer part no. Comment/location Min. Qty LCD Module 1 ASSY LCD (13.3") 3700 6M.44B05.001 1-2 INVERTER T62.088.C.00 970TE 19.21030.151 65.42A01.011 5 1-2 PLT LOGO 7100TE(7300 ACER) 40.46805.151 FOR ACER 50 1-2 7300 HINGE 6M.44B04.001 34.42A13.001+34.42A14.001 50 1-2 ASSY PANEL LCD 13.3” 970T 60.
Table C-1 Level Spare Parts List Description Acer part no. Comment/location Min. Qty CD-ROM 1 ASSY CD-ROM MODULE (14X) 7300 6M.44B01.001 1-2 C.A FPC CD-ROM 14X 970T 50.42A03.001 10 50 1-2 ASSY CD-ROM 14X BZL 970T 60.42A05.001 50 65.42A01.001 FDD 1 ASSY FDD MODELE 7300 6M.44B02.001 1-2 CABLE ASSY FDD 52P 970 50.46802.001 20 1-2 C.A 25/52P 300MM EXT FDD 970 50.46810.002 50 1-2 ASSY FDD L-CASE 050 970 60.46822.003 50 1 ASSY HDD MODULE (IBM) 4GB 6M.44B03.001 56.02834.071+60.
$ S S H Q G L [ ' Schematics This appendix includes the schematic diagrams of the notebook.
Table D-1 Schematics Diagram List Page Description D-34 PCMCIA Controller D-35 PCMCIA Sockets D-36 PCMCIA Socket Power and Interrupt Control D-37 System / Media Board Connector D-38 Internal Keyboard and Touchpad Connector D-39 CRT & LCD Controller D-40 LCD Interface Logics D-41 Isolation Logic and Spare Parts D-2 Service Guide
Schematics D-3
D-4 Service Guide
Schematics D-5
D-6 Service Guide
Schematics D-7
D-8 Service Guide
Schematics D-9
D-10 Service Guide
Schematics D-11
D-12 Service Guide
Schematics D-13
D-14 Service Guide
Schematics D-15
D-16 Service Guide
Schematics D-17
D-18 Service Guide
Schematics D-19
D-20 Service Guide
Schematics D-21
D-22 Service Guide
Schematics D-23
D-24 Service Guide
Schematics D-25
D-26 Service Guide
Schematics D-27
D-28 Service Guide
Schematics D-29
D-30 Service Guide
Schematics D-31
D-32 Service Guide
Schematics D-33
D-34 Service Guide
Schematics D-35
D-36 Service Guide
Schematics D-37
D-38 Service Guide
Schematics D-39
D-40 Service Guide
Schematics D-41
$ S S H Q G L [ ( BIOS POST Checkpoints This appendix lists the POST checkpoints of the notebook BIOS. Table E-1 POST Checkpoint List Checkpoint Description 04h • Determines if the current booting procedure is from cold boot (press reset button or turn the system on), from warm boot (press Ctrl +Alt +Del). Note: At the beginning of POST, port 64 bit 2 (8042 system flag) is read to determine whether this POST is caused by a cold or warm boot.
Table E-1 POST Checkpoint List Checkpoint 24h Description • Tests programmable interrupt controller (8259) • Initializes system interrupt 30h • Enables system shadow RAM 34h • Memory sizing 5Ah • Changes SMBASE, copy SMI Handler. • 56h • Issues 1st software SMI to communicate with PMU. • Initializes the SMI environment.
Table E-1 POST Checkpoint List Checkpoint Description 74h • Serial port testing 78h • Math coprocessor testing 7Ch • Reset pointing device 80h • Set security status 84h • KB device initialization • Set KB led upon setup requests • Enable KB device 86h • Issue 2nd software SMI to communicate with PMU • Enable the use of BIOS Setup, system information. and fuel gauge 6Ch • Tests and initializes FDD Note: The FDD LED should flash once and its head should be positioned.
E-4 Service Guide
