Technical information

9 Chapter 1
Formatter Block Diagram
VCC2,VOFFSET,VBIAS
VERSET GENERATION
RESET ASIC
DMD
0.7” XGA
DATAPATH
FORMATTER
DPF2A
SDRAM B
SDRAM A
ALLEGRO
MOTOR
CONTROL
MICRO
CONTROLLER
CONTROL
FPGA
CONFIG/
SEQUENCE
PROM
CUSTOMER INTERFACE CONNECTOR
VCC2 (DMD)
VCC2 (ASIC)
VOFFSET
VBIAS
VRESET
+5V +12V
CLOCK
OSC
DPF2A CONTROL
VSYNCZ
HSYNCZ
ACTDATA
TFIELD
OLACT
SYNCVAL
LAMP CONTROL&STATUS
COLOR WHEEL INDEX
FPGA CLK
FLASH
PROGRAMMING
HEADER
IIC BUS
HITACHI
DOWNLOAD
HEADER
CLKIN
COLOR
WHEEL
CONTROL
COLOR WHEEL STATUS
CWRSTZ
VOLTAGE ENABLES
BIAS BIN
BIAS/RESET CONTROL
DMD CONTROL
PBUS2
MENORY CONTROL A
MENORY ADDRESS A(12)
MENORY CONTROL B
DMD CONTROL
COLOR
WHEEL
DRIVE
DATA (8)
VSYNCZ, RESETZ
ADDRESS (19)
MBIASRST (16)
INPUTCLK
FPGA CLK
DMD CLK
SDRAM CLK
DATA(0..63)
DMD DATA(0..63)
MENORY ADDRESS A(12)
MENORY ADDRESS B(12)