Specifications

PC/II+p Board Technical Reference Manual 69
MT002615 ©1999-2001, Megatel Computer Corporation
7.26 Timers / Counters
PC/II+p contains the three standard timers/counters, that are compatible to the AT standard 8254. The clock
input for each is tied to a clock of 1.193 MHz, which is derived by dividing the system 14.31818 MHz clock by
12, and which provides a minimum timing resolution of 838 ns.
Timer 0 output is tied to IRQ0 (Interrupt controller 1, level 0).
Timer 1 output is used to initiate a refresh cycle for system memory.
Timer 2 is used to generate signals that produce sound waveforms on the Speaker Output signal.
ISA compatible I/O ports 40h, 41h, 42h and 43h provide access to the three timer counter channels and a
timer counter command mode register. ISA compatible I/O port 61h provides timer counter 2 OUT status in
bit 5 (R only), and timer counter disable/enable control in bit 0 (RW).
For more detailed information, please refer to the Acer Laboratories M1543C datasheet, found in section 2
,
"Reference Documents
" in this document.