Specifications

PC/II+p Board Technical Reference Manual 54
MT002615 ©1999-2001, Megatel Computer Corporation
7.18 PC/104 Bus Interface
PC/II+p provides a 16-bit (or 8-bit) PC/104 bus through on-board connectors J901 and J902. One or more
PC/104 option modules can be attached to PC/II+p via the PC/104 bus connectors.
PC/II+p supports a 64-pin (2x32) PC/104 AB Bus connector (J901), and a 40-pin (2x20) PC/104 CD Bus
connector (J902) — Refer to Figure 5
and Figure 6.
The PC/104 SYSCLK line (ISA Clock) can be configured (via the BIOS) to operate at several speeds
depending upon the requirements of attachments — Refer to Table 23
.
Bus drive for the PC/104 bus (which is ISA bus compatible) has reduced drive requirement — refer to Table
7
.
The PC/104 (ISA) bus may also be configured (via the BIOS) to:
enable or disable port 92H (Reg 43h, bit 7);
set the ISA refresh period (bits 5-4) — refer to Table 24
;
set the 16-bit ISA wait states (bits 3-2) — refer to Table 25
;
set the 16-bit ISA I/O wait states (bits 1-0) — refer to Table 26
.
Pinouts for the PC/104AB connector (J901) and the PC/104CD connector (J902) are included for reference
below — refer to Table 27
and Table 28.
Please refer to the documents, "PC/104 specification – Revision 2.3 – June 1996" and "P996.1 Standard or
Compact Embedded-PC Modules".
NOTE: the term "default" in the tables below indicates the setting that is shipped in the bios unless you
specify otherwise. For utility programs which manipulate these values, please contact megatel Engineering.
Table 23 PC/104 SYSCLK (ISA) Clock Speed Values
CLOCK
SELECT
VALUE
OF REG 42h
BITS 2-0
SPEED FORMULA COMMENT
5.50 MHz
101 PCICLK/6
6.60 MHz
100 PCICLK/5
7.16 MHz
000 (14.318 MHz)/2
8.25 MHz
011 PCICLK/4 Default Speed
11.00 MHz
010 PCICLK/3
16.50 MHz
001 PCICLK/2
NOTES
(1) PCI to ISA Bridge Configuration Space (IDSEL = AD18), Index 42h, register bits 2-0
(2) PCICLK is assumed to be 33.3 MHz. Because PCICLK potentially can be configured to other values (for
example, to 30.0 MHz), the ISA CLOCK selected is actually PCICLK/n as indicated in the table, and the
values in column 2 should be adjusted accordingly.