Specifications

PC/II+p Board Technical Reference Manual 49

PIN NAME PIN# SIGNAL NAME SIGNAL DESCRIPTION

A1-IORDY

a5 IDE Ready

A1-IORDY,A1-DDMARDY#,A1-DSTROBE

A1-IORDY This signal is negated to extend the host

transfer cycle of any host register access (Read or

Write) when the device is not ready to respond to a

data transfer request. If the device requires to extend

the host transfer cycle time at PIO modes 3 and

above, the device shall utilize A1-IORDY.

A1-DDMARDY# is a flow control signal for Ultra DMA

data out bursts. This signal is asserted by the device to

indicate to the host that the device is ready to receive

Ultra DMA data out bursts. The device may negate A1-

DDMARDY# to pause an Ultra DMA data out burst.

A1-DSTROBE is the data in strobe signal from the

device for an Ultra DMA data in burst. Both the rising

and falling edge of A1-DSTROBE latch the data from

A1-DD(15:0) into the host. The device may stop

generating A1-DSTROBE edges to pause an Ultra

DMA data in burst.

A1-INTRQ

d6 IDE Interrupt

This signal is used by the selected device to interrupt

the host system. When the IEN bit is cleared to zero,

and the device is selected,

A1-INTRQ is enabled through a tri-state buffer and

driven either asserted or negated. When the IEN bit is

set to one, or the device is not selected, the A1-INTRQ

signal is in a high impedance state. When asserted,

this signal is negated by the device within 400 ns of

the negation of A1-DIOR# that reads the Status

device within 400 ns of the negation of

A1-DIOW# that writes the Command register. When

the device is selected by writing to the Device/Head

asserted within 400 ns of the negation of A1-DIOW#

that writes the Device/Head register. When the device

is deselected by writing to the Device/Head register

while an interrupt is pending, A1-INTRQ is negated

within 400 ns of the negation of

A1-DIOW# that writes the Device/Head register. For

devices implementing the Overlapped feature set, if

interrupts are being disabled using IEN at the same

instant that the device asserts A1-INTRQ, the

minimum pulse width of A1-INTRQ should be at least

40 ns.