Specifications

PC/II+p Board Technical Reference Manual 36

7.5 Cpu Processor

PC/II+p contains a 321-Pin socket for a Socket 7 Processor. Socket 7 specification is backward compatible

with Socket 5 and with many 296-Pin SPGA and CPGA processors. Bus speeds up to 66 MHz are supported

by the Socket 7.

There are potentially many Socket 7 processors that are available, and PC/II+p has been designed to

support a standard set of LOW POWER processors which operate at a standard set of voltages and speeds,

that are available from multiple vendors. The list of supported processors is given in the following table.

Table 10 Supported Processors List (v2.04)

MANUF PROCESSOR PART CORE FREQ BUS FREQ MAX POWER

AMD K6-2E/233AMZ 233 MHz 66 MHz 5.4 w

INTEL PENTIUM FV80503CSM66166 166 MHz 66 MHz 8.5 w

INTEL PENTIUM FV80503CSM66266 266 MHz 66 MHz 10.7 w

NOTES

(1) MAX POWER is as stipulated by the manufacturer; typically this value will be much lower.

(2) User-supplied processors MUST be certified by Megatel; contact megatel Engineering or your

representative for more information.

You may also order the PC/II+p to contain just the Socket 7 socket on-board, if you intend to supply the

processor in the field. Contact Megatel, a distributor or retailer for assistance in making any special order.

Any processor used on this product MUST be certified by Megatel to maintain your product's warranty -

please contact your representative or Megatel Engineering for more information.

All of the supported processors operate the Host local bus at 66 MHz, and each has both common features

with the others, and features unique to it. All processors support all standard operating software such as

Linux, Windows or DOS.

Socket 7 processors such as the Pentium are superscalar (pipelined) processors, with multiple pipelines

each containing a varying number of execution stages. They contain an integrated Floating-Point unit which

may be separately pipelined, and may contain a separate MMX execution unit or one which is combined with

the Floating Point Unit. They are architecturally decoupled to improve decoding and execution overlap, and

provide a number of features to enhance performance including Out-of-Order execution, Branch Prediction,

Data Dependency Removal, Register Renaming and Data Forwarding, and Speculative Execution.

Socket 7 Processors include on-chip cache (L1) of varying size and organization depending upon the internal

operating frequency of the processor. INTEL processors contain split caches totaling 32 KB (one cache for

code, and a write-back cache for data). AMD processors contain larger split caches totaling 64 KB (one

cache for code, and a write-back cache for data). Additional cache or buffering for Branching, code and

decoding may be present.

Floating Point units support floating-point operations and data types which usually conform to IEEE 754 or

IEEE 854 specifications. MMX operations conform to published Intel MMX standards.

For complete processor specifications, please refer to the Intel & AMD processor datasheets listed in the

section "Datasheets

" in this document.