User Guide

areallowed.IfthenIRQ is u s ed to m onitorthecu rrent s tate,therewillbeas light delay cau s ed
by theinternalhardwarefrom when theev ent actu ally occu rs to when thetrans ition occu rs on
the nIR Q . T he tim e from entering T X s tate to w hen the nIR Q w ill trans ition is 13 μ s . If a G PIO
is program m edforT X s tateoru s ed as controlfora trans m it/receiv es witch (T R s witch),there
is no delay.
Figure11.S T AR T _T X com m andsand T im ing
RX State
T heRX s tateis u s ed whenev erthedev iceis requ ired to receiv edata.It is enteredu s ingeither
theST ART _ R X orC H AN G E_ ST AT E com m ands .W ith theST ART _ R X com m and,thenext
s tatecan bedefinedto ins u reoptim altim ing.W hen eithercom m and is s ent to enterR X s tate,
an internals equ encerau tom atically takes careofallactions requ ired to m ov ebetween s tates
with no additionalu s ercom m ands needed.T hes equ encercontrolledev ents can inclu de
enablethedigitaland analogL DOs ,s tart u p thecrys talos cillator,enablePL L ,calibrateV CO,
enablereceiv ercircu its ,and enablereceiv em ode.T hedev icewillals o au tom atically s et u p all
receiv erfeatu res s u ch as packet handlingbas ed u pon theinitialconfigu ration ofthedev ice.
RX and TX FIFOs
T wo 64-byteFIFOs areintegratedinto thechip,oneforRX and oneforT X .W ritingto
com m andregis ter66h loads data into theT X FIFO and readingfrom com m andregis ter77h
reads data from theR X FIFO.Forpacket lengths greaterthan 64bytes ,
RX _ FIFO_ AL M OST _ FU L L and T X _ FIFO_ AL M OST _ EM PT Y s tatu s bits and interru pts can
beu s edto m anagetheFIFO.T hethres holdv alu eforthes ecan beconfigu redv iatheW D S
radio configu ration application G U I.T hem axim u m payloadlength s u pported in packet handler
m odeis 255bytes .
Packet Handler
T heRF m odu leinclu des integrated packet handlerfeatu res s u ch as pream bleand s yncword
detection as wellas CR C calcu lation.T his allows thechip to qu alify and s ynchronizewith