390 Series Notebook Computer Service Guide PART NO.: 49.43A02.001 DOC. NO.
Copyright Copyright 1997 by Acer Incorporated. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without the prior written permission of Acer Incorporated.
About this Manual Purpose This service guide aims to furnish technical information to the service engineers and advanced users when upgrading, configuring, or repairing the 390 series notebook computer. Manual Structure This service guide contains technical information about the 390 series notebook computer. It consists of three chapters and five appendices. Chapter 1 System Introduction This chapter describes the system features and major components.
Appendix D Schematics This appendix contains the schematic diagrams for the system board. Appendix E BIOS POST Checkpoints This appendix lists and describes the BIOS POST checkpoints. Conventions The following are the conventions used in this manual: Text entered by user Represents text input by the user. Screen messages Denotes actual messages that appear onscreen. , , , etc. Represent the actual keys that you have to press on the keyboard.
Table of Contents Chapter 1 System Introduction 1.1 Overview ............................................................................................................. 1-1 1.2 System Board Layout........................................................................................... 1-2 1.2.1 Mainboard............................................................................................. 1-2 1.2.2 CPU Board..................................................................................
1.5 1.6 1.4.24 LCD .....................................................................................................1-21 1.4.25 AC Adapter ..........................................................................................1-22 Software Configuration and Specification............................................................1-23 1.5.1 BIOS....................................................................................................1-23 1.5.2 Drivers, Applications and Utilities ...
2.6 2.5.3 Pin Configuration .................................................................................2-78 2.5.4 Pin Descriptions ...................................................................................2-79 YMF715B-S ........................................................................................................2-81 2.6.1 Features...............................................................................................2-81 2.6.2 Pin Diagram ............................
Appendices Appendix A Model Number Definition Appendix B Exploded View Diagram Appendix C Spare Parts List Appendix D Schematics Appendix E BIOS POST Checkpoints viii
List of Figures 1-1 PCB No. 96183-1A Mainboard Layout (Top) ........................................................ 1-2 1-2 PCB No. 96183-1A Mainboard Layout (Bottom) ................................................... 1-3 1-3 PCB No. 96534-SE CPU Board Layout (Top)....................................................... 1-4 1-4 PCB No. 96534-SE CPU Board Layout (Bottom).................................................. 1-4 1-5 PCB No. 97355-1 Audio Board............................................
x 4-11 Removing the LED Cover ...................................................................................4-12 4-12 Removing the Heat Sink Assembly .....................................................................4-12 4-13 Unplugging the Display Cable .............................................................................4-13 4-14 Removing the Display Hinge Screws ..................................................................4-13 4-15 Removing the Display Hinge Screws ........
List of Tables 1-1 CPU Mounting Reference Table........................................................................... 1-5 1-2 SW1 Switch Settings ........................................................................................... 1-8 1-3 Memory Address Map .......................................................................................... 1-9 1-4 Interrupt Channel Map .........................................................................................
xii 1-35 Hard Disk Standby Mode Conditions and Descriptions ........................................1-28 1-36 Location of Drivers in the System Utility CD........................................................1-29 1-37 Location of Applications in the System Utility CD ................................................1-30 1-38 Environmental Requirements..............................................................................1-33 1-39 Mechanical Specifications...................................
C h a p t e r 1 System Introduction 1.1 Overview This computer combines high-performance, versatility, power management features and multimedia capabilities with unique style and ergonomic design. This computer was designed with the user in mind.
1.2 System Board Layout 1.2.1 Mainboard Figure 1-1 1-2 PCB No.
Figure 1-2 PCB No.
1.2.2 CPU Board Figure 1-3 PCB No. 96534-SE CPU Board Layout (Top) Figure 1-4 PCB No.
The following table is a reference when mounting1 the CPU. Table 1-1 CPU Mounting Reference Table Volt. CPU Ratio Freq R4 R6 R8 R11 R20 R22 R24 R26 RX14 RY1 RX6 RX9 RX11 RX12 UX2 UX3 P55C-133MHz 2.5V 133=66x2 V X V X V X X V V X V X X X X X P55C-150MHz 2.5V 150=60x2.5 V X V V X X V V V X V X X X X X P55C-166MHz 2.5V 166=66x2.5 V X V X X X V V V X V X X X X X TLMK-200MHz 1.
1.2.5 Keyboard/Touchpad Board Figure 1-7 PCB No. 97349-1 Keyboard/Touchpad Board (Top View) Figure 1-8 PCB No.
1.
BOTTOM VIEW CN24 CN23 DIMM CN23 CN24 DIMM Modem connector Modem connector DIMM sockets Figure 1-10 Jumpers and Connectors (Bottom View) The following tables list the switch settings for SW1. Table 1-2 SW1 Switch Settings ON OFF Switch 1 (Logo Screen) OEM Acer Switch 2 (Password) Bypass Check Germany U.S.
1.4 Hardware Configuration and Specification 1.4.1 Memory Address Map Table 1-3 Memory Address Map Address Range Definition Function 000000 - 09FFFF 640 KB memory Base memory 0A0000 - 0BFFFF 128 KB video RAM Reserved for graphics display buffer 0C0000 - 0CBFFF Video BIOS Video BIOS 0F0000 - 0FFFFF 64 KB system BIOS System BIOS 100000 - top limited Extended memory SIMM memory FE0000 - FFFFFF 256 KB system ROM Duplicate of code assignment at 0E0000-0FFFFF 1.4.
1.4.3 DMA Channel Map Table 1-5 DMA Channel Map Controller Channel Address Function 1 1 1 1 2 2 2 2 0 1 2 3 4 5 6 7 0087 0083 0081 0082 Cascade 008B 0089 008A Audio (option) / Audio Audio (option) / ECP / Audio / FIR Diskette Audio (option) / ECP / FIR Cascade Not support Not support Not support / Audio 1.4.
1.4.5 Processor Table 1-7 Processor Specifications Item Specification CPU type P55C-133/150/166 CPU package TCP Switchable processor speed (Y/N) Yes Minimum working speed 0MHz CPU core voltage 2.0V/2.45V/1.8V CPU I/O voltage 2.5V/3.3V/2.5V 1.4.6 BIOS Table 1-8 BIOS Specifications Item Specification BIOS vendor Acer BIOS version V3.
• 16MB (2M*8x8) • 32MB (4M*16x4) • 64MB (8M*8x8) • Expansion RAM module speed/voltage/package: 60ns/3.3v/TSOP EDO • EDO and fast-page mode DIMMs may be used together in a memory configuration. The following table lists all possible memory configurations. Table 1-9 1.4.
1.4.9 Video Memory Table 1-10 Video RAM Configuration Item Specification DRAM or VRAM DRAM(EDO type) Fixed or upgradeable Fixed Memory size/configuration 2MB (256K x 16 x 4pcs) Memory speed 50ns Memory voltage 3.3V Memory package TSOP 1.4.10 Video Table 1-11 Video Hardware Specification Item Specification Video chip C&T65555 Working voltage 3.3V 1.4.10.
1.4.10.
1.4.12 Serial Port Table 1-15 Serial Port Configurations Item Specification Number of serial ports 1 16550 UART support Yes Connector type 9-pin D-type Location Rear side Selectable serial port (by BIOS Setup) • • • 1.4.
Table 1-17 PCMCIA Specifications Item Specification Chipset TI 1250A Supported card type Type-II / Type-III Number of slots Two Type-II or one Type-III Access location Left side ZV (Zoomed Video) port support Yes 1.4.
1.4.16.1 Windows 95 Keys The keyboard has two keys that perform Windows 95-specific functions. See Table 1-26. Table 1-20 Windows 95 Key Descriptions Key Description Windows logo key Application key 1.4.17 Start button. Combinations with this key performs special functions, e.g.
1.4.18 HDD Table 1-22 HDD Specifications Item Vendor & Model Name Specification Hitachi DK225A-21 IBM DTNA22160 IBM DDLA21620 Capacity (MB) 2160 2160 1620 Bytes per sector 512 512 512 Logical heads 16 16 16 Logical sectors 63 63 63 Logical cylinders 4889 4200 3152 Physical read/write heads 6 6 3 Disks 3 3 2 Spindle speed (RPM) 4464 4000 4000 Buffer size (KB) 128 96 96 Interface ATA-3(IDE) ATA-2 ATA-2 Data transfer rate (disk-buffer, Mbytes/s) 5.7 ~ 9.
1.4.20 Battery Table 1-24 Battery Specifications Item Specification Battery gauge on screen Yes, by hotkey Yes, by hotkey Vendor & model name Toshiba BTP-031 Sony BTP-T31 Battery type NiMH Li-Ion Cell capacity (mAH) 3500 1400 Cell voltage (V) 1.2 3.6 Number of battery cell 9-cell 9-Cell Package configuration 9 serial 3 serial, 3 parallel Package voltage (V) 10.8 10.8 Package capacity (WAH) 3500 4200 Second battery No No 1.4.
Table 1-25 Charger Specifications Item Specification Vendor & model name Ambit T62.069.C.00 Input voltage (from adapter, V) 0-24V Output current (to DC/DC converter, A) 3 (max.) Battery Low Voltage Battery Low 1 level (V) 10.16 (typ., for NiMH) 8.566 (typ., for LIB) Battery Low 2 level (V) 10.279 (typ., for NiMH) 8.185 (typ., for LIB) Battery Low 3 level (V) 9.137 (typ., for NiMH) 7.709 (typ., for LIB) Charge Current Background charge (charge even system is still operative, A) 0.8 (typ.
1.4.23 DC-AC Inverter DC-AC inverter is used to generate very high AC voltage, then supply to LCD CCFT backlight use, and is also responsible for the control of LCD brightness. Avoid touching the DC-AC inverter area while the system unit is turned on. Table 1-27 DC-AC Inverter Specifications Item Specification Vendor & model name Ambit T62.071.C.00 Input voltage (V) 6.8(in.) - 22(max.) - - 750 (max.) Output voltage (Vrms, no load) 1000 (min.) - 1600 (max.
1.4.25 AC Adapter Table 1-29 AC Adapter Specifications Item Vendor & model name Specification Delta ADP-45GB Rev. E3, E5 Input Requirements Nominal voltages (Vrms) 90 - 264 Nominal frequency (Hz) 47 - 63 Frequency variation range (Hz) 47 - 63 Maximum input current (A, @90Vac, full load) 1.5 A Inrush current The maximum inrush current will be less than 50A and 100A when the adapter is connected to 115Vac(60Hz) and 230Vac(50Hz) respectively.
1.5 Software Configuration and Specification 1.5.1 BIOS The BIOS is compliant to PCI v2.1, APM v1.2, E-IDE and PnP specification. It also defines the hotkey functions and controls the system power-saving flow. 1.5.1.1 Keyboard Hotkey Definition The notebook supports the following hotkeys. Table 1-30 Hotkey Hotkey Descriptions Icon Function Description Fn-Esc Hotkey Escape Exits the hotkey control. Fn-F1 Hotkey Help Displays the hotkey list and help. Press | to exit the screen.
1.5.1.2 MultiBoot The system can boot from the FDD, External FDD, HDD, CD-ROM. The user can select the desired booting process to boot the system. If the CD-ROM is bootable, the BIOS will override the other process to boot the system directly. 1.5.1.3 Power Management This computer has a built-in power management unit that monitors system activity.
ON MODE Normal full-on operation STANDBY MODE The computer consumes very low power in standby mode. memory until battery is drained. Data remain intact in the system Warning: Unstored data is lost when you turn off the computer power in standby mode or when the battery is drained.
LIGHT GREEN MODE The notebook consumes very low power in light green mode. Data and I/O connections remain intact in the system memory until battery is drained. Table 1-32 Light Green Mode Conditions and Descriptions Condition Description The condition to enter Light Green Mode • • PCMCIA I/O Card detected and occupy resources (Non Cardbus mode). HPM timer times out or cover close or APM standby / suspend function calls. The condition of Light Green Mode • • Issue a beep.
Table 1-33 Hibernation Mode Conditions and Descriptions Condition Description The condition to enter Hibernation Mode There are two necessary conditions for the computer to enter standby mode: • Heuristic Power Management Mode must be set to [ENABLED]. • System Sleep State must be set to [HIBERNATION]. • The hibernation file created by Sleep Manager must be present and valid.
HARD DISK STANDBY MODE The hard disk enters standby mode when there are no disk read/write operations within the period of time determined by the computer’s HPM unit. In this state, the power supplied to the hard disk is reduced to a minimum. The hard disk returns to normal once the computer accesses it. Table 1-35 Hard Disk Standby Mode Conditions and Descriptions Condition Description The condition to enter HDD Standby Mode Display Standby HPM timer times-out or LCD cover is closed.
The following processes are the basic methods used to implement the LCD brightness AutoDim. 1. If the original brightness is over 75% and the AC power is on-line, the BIOS will change the brightness to 75% after the AC power is off-line. 2. If the original brightness is below 75%, the brightness maintains the same level even if the AC power is off-line. 3. If the brightness is already changed by the hotkey under DC power, it will not be changed after the AC power is plugged in. 4.
To re-install applications under Windows 95, click on Start, then Run…. Based on the location of the application, run the setup program to install the application.
Figure 1-12 System Introduction AMP LM4836 AUD BD Conn. AUDIO YMF715 Serial Port ISA Bus ALI M1533 Internal AUD BD FDD Conn. Conn. Super I/O SMC FDC 37C672 USB Conn. FIR control BIOS ROM Battery Conn. SMB Bus KBC M38813 VGA C&T 65555 Charger Conn. System CD-ROM & HDDD Conn. DIMM2 Socket DIMM1 Socket 1.6.1 PCI Bus ALI M1531 Block Diagrams PCMCIA TI PCI1250A Cache Tag Ram CPU Bus CPU P55C 1.
Figure 1-13 1-32 SGRAM CLK DIMM2 DIMM1 72 38813 MODEM 37C672 YMF715 65555 48MHZ 65555 PCI1250 1533 1531 1533 USB M1531 CACHE CPU 14.318M CPU CLK PCI CLK DIMM2 SMB BUS DIMM1 CLK GEN CY2272 M1533 1.6.
1.7 Environmental Requirements Table 1- 38 Environmental Requirements Item Specification Temperature Operating (ºC) +5~ +35 Non-operating(ºC) -20 ~ +60 Humidity Operating (non-condensing) 20% ~ 80% Non-operating (non-condensing) 20% ~ 80% Operating Vibration (unpacked) Operating 5 - 25.6Hz, 0.38mm; 25.6 - 250Hz, 0.5G Sweep rate 0.5 octave / minute Number of test cycles 2 / axis (X,Y,Z) Non-operating Vibration (unpacked) Non-operating 5 - 27.1Hz, 0.6G; 27.1 - 50Hz, 0.
1.8 Mechanical Specifications Table 1-39 Mechanical Specifications Item Specification Weight FDD model CD-ROM model (includes battery) 2.77 kg. (6.11 lb.) 2.8 kg. (6.2 lb.) Dimensions (main footprint) WxDxH 311.5mm x 236/246mm x 46.5mm (12.26” x 9.29”/9.69” x 1.
C h a p t e r 2 Major Chips Description This chapter discusses the major chips used in the notebook.
2.1 PCI 1250A The Texas Instruments PCI1250A is a high-performance PC Card controller with a 32-bit PCI interface. The device supports two independent PC Card sockets compliant with the 1995 PC Card Standard. The PCI1250A provides a rich featured set which make it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1995 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.
• Supports Burst Transfers to Maximize Data Throughput on both PCI Buses • Supports Serialized IRQ with PCI Interrupts • 8-Way Legacy IRQ Multiplexing • System Interrupts can be Programmed as PCI-style or ISA IRQ-style • ISA IRQ interrupts can be Serialized onto a single IRQSER pin • EEPROM Interface for Loading Subsystem ID and Subsystem Vendor ID • Pipelined Architecture allows Greater than 130 Mbytes per second throughput from CardBus to PCI and from PCI to CardBus • Supports Zoom Video wi
2.1.2 Block Diagram A simplified block diagram of the PCI1250 is provided in following figure. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI & ISA signaling. The ring indicate terminal is included in the interrupt interface, since it's function is to perform system wake-up on incoming PC Card modem rings.
2.1.3 Terminal Functions This section describes the PCI1250A terminal functions. The terminals are grouped in tables by functionality such as PCI system function, power supply function, etc. for quick reference. The terminal numbers are also listed for convenient reference. Table 2-2 PCI1250 Terminal Functions Name No.
Table 2-2 PCI1250 Terminal Functions Name No. I/O Type Function PCI Address and Data Terminals PCI address data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31:0 contain a 32-bit address or other destination. During the data phase AD31 0 contain data.
Table 2-2 PCI1250 Terminal Functions Name No. I/O Type Function PCI Interface Control Terminals DEVSE V20 I/O PCI device select. The PCI1250A asserts this signal to claim a PCI cycle as the target device. As a PCI initiator on the bus. the PCI1250A monitors this signal until a target responds. If no target responds before time-out occurs, then the PCI1250A will terminate the cycle with an initiator abort. FRAME T19 I/O PCI cycle frame. This signal is driven by the initiator of a bus cycle.
Table 2-2 PCI1250 Terminal Functions Name No. I/O Type Function STOP T17 I/O PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI bus tranaction. This signal is used for target disconnects and is commonly asserted by target devices which do not support burst data transfers. TRDY U20 I/O PCI target ready. TRDY indicates the primary bus target s ability to complete the current data phase of the transaction.
Table 2-2 PCI1250 Terminal Functions Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 No. K03 J02 J04 H02 G01 W08 Y07 V07 J01 J03 H01 H03 G02 V08 W07 Y06 E19 E20 G18 G19 H18 B07 C08 A08 G17 F19 F20 F19 H19 A07 B08 D09 I/O Type I/O Function Card Data. 16-bit PC Card data lines. D15 is the most significant 16-Bit PC Card Interface Control Terminals (Slot A And Slot B) BVD1 (STSCHG/RI) Slot A3 Slot B4 V06 A09 Battery Voltage Detect 1.
Table 2-2 PCI1250 Terminal Functions Name BVD2 (SPKR) No. Y05 D10 I/O Type I Function Battery Voltage Detect 2. Generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost.
Table 2-2 PCI1250 Terminal Functions Name IOWR No. M02 C19 I/O Type O Function I/O Write IOWR is driven low by the PCI1250A to strobe write data into 16-bit l/O PC Cards during host l/O write cycles. DMA Read. This pin is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1250A asserts this signal during transfers from host memory to the PC Card. OE L03 C20 O Output Enable.
Table 2-2 PCI1250 Terminal Functions Name WE No. P03 D16 I/O Type O Function Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also use for memory PC Cards that employ programmable memory technologies. DMA terminal count. This pin is used as TC during DMA operations to a 16-bit PC Card which supports DMA. The PC1031 asserts this signal to indicate terminal count for a DMA read operation. WP (IOIS16) U07 B09 I Write protect.
Table 2-2 PCI1250 Terminal Functions Name No. I/O Type Function CRSST W01 C13 I/O CardBus PC Card Reset. This signal is used to bring CardBus PC Card specific registers, sequencers, and signals to a known state. When CRST is asserted, all CardBus PC Card signals must be 3-statedt and the PCI1250A will drive these signals to a valid logic level. Assertion may be asynchronous to the CCLK. But deassertion must be synchronous to the CCLK. CCLKRUN U07 B09 O CardBus PC Card Clock Run.
Table 2-2 PCI1250 Terminal Functions Name No. I/O Type Function CC/BE3 CC/BE2 CC/BE1 CC/BE0 Y02 T03 N01 K01 B12 D14 B19 D20 I/O CardBus Bus Commands and Byte Enables. The command and byte enable signals are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3:0 defines the bus command. During the data phase, this four-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32bit data bus carry meaningful data.
Table 2-2 PCI1250 Terminal Functions Name No. I/O Type Function CINT Y04 A10 I CardBus interrupt. This signal is asserted low by a CardBus PC Card to request interrupt servicing from the host. CIRDY T02 A16 I/O CardBus initiator ready. CIRDY indicates the CardBus initiator's ability to complete the current data phase of the transaction. A data phase is completed upon a rising edge of CCLK where both CIRDY and CTRDY are asserted.
Table 2-2 PCI1250 Terminal Functions Name No. I/O Type Function System Interrupt Terminals GPIO3/INTA V13 I/O GPI03/lNTA Parallel PCI Interrupt. This terminal can be connected to an available PCI interrupt if parallel PCI interrupts are used, and the PCI1250A will output PCI INTA through this terminal. Refer to the Interrupt Subsystem description in this document for details on interrupt signaling.
Table 2-2 PCI1250 Terminal Functions Name CLOCK No. U12 I/O Type I/O Function 3-Line Power Switch Clock. Information on the DATA line is sampled at the rising edge of CLOCK. This terminal defaults to an input, but can be changed to a PCI1250A output by using the P2CCLK bit in the I/O System Control Register. The TPS2206 defines the maximum frequency of this signal to be 2MHz. If a system design defines this terminal an output, then this terminal requires an external pull-up resister.
Table 2-2 PCI1250 Terminal Functions Name No. I/O Type Function PC/PCI DMA Terminals PCREQ/ IRQMUX7 Y12 O PC/PCI DMA Request. This signal is used to request DMA transfers as DREQ in a system supporting the PC. PCI DMA scheme. IRQMUX7. When this terminal is configured for IRQMUX7, it provides the IRQMUX7 interrupt output of the interrupt mux, and can be mapped to any of 15 ISA type IRQs. The IRQMUX7 signal takes precedence over PCREQ, and should not be enabled in a system using PC/PCI DMA.
Table 2-2 PCI1250 Terminal Functions Name SPKROUT No. Y10 Major Chips Description I/O Type O Function Speaker Output. This signal is the output to the host system that can carry the SPKR or CAUDIO signal through the PCI1250A from the PC Card interface. This signal is driven as the exclusive OR combination of card SPKR//CAUDIO inputs.
2.2 Aladdin IV (M1531/M1533) The Aladdin-IV is the succeeding generation chipset of Aladdin-III from Acer Labs. It maintains the best system architecture (two-chip solution) to achieve the best system performance with the lowest system cost (TTL-free). The Aladdin-IV consists of two BGA chips to give the 586-class system a complete solution with most up-to-date features and architecture for multimedia/ multithreading OS and software applications.
2.2.1.1 • • Features Supports all Intel/Cyrix/AMD/TI/IBM 586 processors. Host bus at 83.3, 75, 66, 60 and 50 MHz at 3.3V/2.5V Supports Linear Wrap mode for Cyrix M1 and M2 • Write-Allocation feature for K6 • Pseudo-Synchronous PCI bus access (CPU bus: 75 MHz - PCI bus: 30 MHz, CPU bus: 83.
• Supports the most flexible six 32-bit populated banks of DRAM for easy DRAM upgrade • Supports SIMM and DIMM • Synchronous/Pseudo Synchronous 25/30/33MHz 3.
2.2.1.
2.2.1.3 Signal Descriptions Table 2-3 M1531 Signal Descriptions Signal Type Description Host Interface 3.3V/2.5V A[31:3] I/O Group A BEJ[7:0] I Group A ADSJ I Group A BRDYJ O Group A NAJ O Group A AHOLD O Group A EADSJ O Group A BOFFJ O Group A HITMJ I Group A MIOJ I Group A DCJ I Group A WRJ I Group A HLOCKJ I Group A CACHEJ I Group A 2-24 Host Address Bus Lines. A[31:3] have two functions.
Table 2-3 M1531 Signal Descriptions Signal KENJ/INV Type O Group A SMIACTJ I Group A HD[63:0] I/O Group A MPD[7:0] I/O Group C RASJ[7] / SRASJ[0] O RASJ[6] / SCASJ[0] O RASJ[5:0] O Group C Group C Group C CASJ[7:0] / DQM[7:0] O MA[11:2] O Group C Group C MAA[1:0] O Group C MAB[1:0] O Group C MWEJ[0] O Group C MD[63:0] I/O Group C CLKEN[0]/ REQJ[4] I/O Group C Major Chips Description Description Cache Enable Output. This signal is connected to the CPU's KENJ and INV pins.
Table 2-3 M1531 Signal Descriptions Signal CLKEN[1]/ GNTJ[4] Type Description Group C SDRAM Clock Enable Copy 1 or PCI Master Grant. This signal is used as SDRAM clock enable copy 1 to do self refresh during suspend. It can also be used as grant signal of the fifth PCI master. This function is controlled by Index -5Dh bit 1. O Secondary Cache Interface 3.3V/2.
Table 2-3 M1531 Signal Descriptions Signal DEVSELJ Type I/O Group B IRDYJ I/O Group B TRDYJ I/O Group B STOPJ I/O Group B LOCKJ I/O Group B REQJ[3:0] I Group B GNTJ[3:0] O Group B PHLDJ I Group B PHLDAJ PAR O Description Device Select. When the target device has decoded the address as its own cycle, it will assert DEVSELJ. Initiator Ready. This signal indicates the initiator is ready to complete the current data phase of transaction. Target Ready.
Table 2-3 M1531 Signal Descriptions Signal Type Description Power Pins VCC_A P Vcc 3.3V or 2.5V Power for Group A. This power is used for CPU interface and L2 control signals. If this power connects to 3.3V, the relative signals will output 3.3V and accept 3.3V input. If this power connects to 2.5V, the relative signals will output 2.5V and accept 2.5V input. VCC_B P Vcc 3.3V Power for Group B. This power is used for PCI interface and Tag signals. It must connect to 3.3V.
Table 2-4 No. M1531 Numerical Pin List Name Type No. Name Type No.
Table 2-4 No. M1531 Numerical Pin List Name Type No. Name Type No.
Table 2-4 No. M1531 Numerical Pin List Name Type No. Name Type No.
Table 2-4 No. M1531 Numerical Pin List Name Type No. Name Type No.
Table 2-4 No. M1531 Numerical Pin List Name Type No. Name Type No.
Table 2-4 No. M1531 Numerical Pin List Name Type No. Name Type No.
The chip provides two extra IRQ lines and one programmable chip select for motherboard Plug-and-Play functions. The interrupt lines can be routed to any of the available ISA interrupts. The on-chip IDE controller supports two separate IDE connectors for up to four IDE devices providing an interface for IDE hard disks and CD ROMs. The Ultra 33 specification (that supports the 33 MB/second transfer rate) has been implemented at this IDE controller.
• Independent programmable level/edge triggered channels • Counter/Timers • 8254 compatible timers for System Timer, Refresh Request, Speaker Output Use • Distributed DMA supported • 7 DMA Channels can be arbitrarily programmed as distributed channel • Serialized IRQ supported • Quiet/Continuous mode • Programmable (default 21) IRQ/DATA frames • Programmable START frame pulse width • Plug-and-Play port supported • One programmable chip select • Two steerable interrupt request lines • Built-in keyb
− Hard disk − Floppy − Serial ports − Parallel port − Keyboard − Six programmable I/O groups − Three programmable memory spaces • Provides hot plugging events detection − CRT connector − AC power − Docking insert − Eject − Setup button − Hot key press • Multiple external wakeup events of Standby mode − Power button − Cover open − Modem ring − RTC alarm − EXTSW − DRQ2 • Suspend wakeup detected − Hot key − Modem ring − RTC alarm − Cover open − Docking insert − Power button − USB events − IRQ − EJECT − ACPWR −
• L2 cache power down and PCI CLKRUN control logic supported • 21 general purpose input signals, 24 general purpose output signals, 20 general purpose input/output signals • 16 external expandable general purpose inputs, 16 external expandable general purpose outputs • LCD control • All registers readable/restorable for proper resume from Suspend state • Built-in PCI IDE controller • Supports Ultra 33 Synchronous DMA Mode transfers up to Mode 2 Timing (33 MB/sec) • Supports PIO Modes up to Mode 5 timings,
2.2.2.
2.2.2.3 Numerical Pin List Table 2-5 No. M1533 Numerical Pin List Name Type No. Name Type No.
Table 2-5 No. M1533 Numerical Pin List Name Type No. Name Type No.
Table 2-5 No. M1533 Numerical Pin List Name Type No. Name Type No.
Table 2-5 No. M1533 Numerical Pin List Name Type No. Name Type No.
Table 2-5 M1533 Numerical Pin List No. Name Type No.
Table 2-5 M1533 Numerical Pin List No. Name Type No. Name Type R20 GPO13/IRQ1O O V7 LA22 I/O R19 GPO14/IRQ12O O T7 LA23 I/O R18 GPO15/IRQ0 O M19 LBJ I R17 GPO16APICCSJ O M20 LID I R16 GPO17/APICGNTJ O K16 LLBJ I P17 GPO18/BIOSA16 O V6 M16J I/O P16 GPO19/BIOSA17 O W9 MEMRJ I/O Table 2-5 No. M1533 Numerical Pin List Name Type No. Name Type No.
Table 2-5 No. M1533 Numerical Pin List Name Type No. Name Type No.
2.3 FDC37C672 The FDC37C672 is a 100-pin enhanced super l/O controller with Fast IR. 2.3.1 Features • 5 Volt Operation • PC97 Compliant • ISA Plug and Play Compatible Register Set • Intelligent Auto Power Management • Shadowed Write-only Registers for ACPI Compliance • System Management Interrupt, Watchdog Timer • 2.
• Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface • Asynchronous Access to Two Data Registers and One Status Register • Supports Interrupt and Polling Access • 8it Counter Timer • Port 92 Support • 8042 P12 and P16 Outputs • Serial Ports • Two Full Function Serial Ports • High Speed NS16C550 Compatible UARTs with Send/Receive 16yte FlFOs • Supports 230k and 460k Baud Programmable Baud Rate Generator Modem Control Circuitry • 480 Address and Eight IRQ Options • Infrared Port • Multiprotoco
2.3.2 General Description The FDC37C67x with Consumer IR and IrDA v 1.1 support incorporates a keyboard interface, SMC's true CMOS 765B floppy disk controller, advanced digital data separator, two 16C550 compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP, on-chip 24 mA AT bus drivers, two floppy direct drive support, Intelligent power management and SMI support.
2.3.
Figure 2-5 FDC37C67 (QFP) Pin Diagram Major Chips Description 2-51
2.3.4 Pin Descriptions Table 2-6 FDC37C67 Pin Descriptions Pin No.
Table 2-6 FDC37C67 Pin Descriptions Pin No.
Table 2-6 FDC37C67 Pin Descriptions Pin No./QFP Pin Name Type Symbol Buffer Type 78 Paper End 1 PE I 77 Printer Selected 1 SLCT I 81 Error at Printer 1 nERROR I Keyboard/Mouse Interface (6) 56 Keyboard Data .
2.3.5 Description of Multifunction Pins Table 2-7 Pin No./QFP 2 FDC37C67 Multifunction Pin Descriptions Original Function DRVDEN1 Alternate Function 1 IR MODE Alternate Function 2 IRRX3 Default DRVDEN1 Controlled by IRMODSEL(LD8:CRC0.0) and IRRX3SEL(LD8:CRC0.4) 32 PCICLK IRQ4 PCICLK 33 SERIRQ IRQ3 SERIRQ Controlled by SERIRQSEL(LD8:CRCO.2) 51 nDACK3 8042 P16 nDACK3 52 DRQ3 8042 P12 DRQ3 Controlled by DMA3SEL(LD8:CRCO.
2.3.
2.4 65555 2.4.
• • Display centering and stretching features for optimal fit of V(iA graphics and text on 800x600 and 1024x768 panels Simultaneous Hardware Cursor and Pop-up Window • 64x64 pixels by 4 colors • 128x128 pixels by 2 colors • Game Acceleration • Source Transparent BLT • Destination Transparent BLT • Double buffer support for YUV and 15/16bpp Overlay Engine • Instant Full Screen Page Flip • Read back of CRT Scan line counters • Optimized for High-Performance Flat Panel Display at 3.
2.4.
• Software Support • Dedicated Software Applications Engineer • BBS Support for Software Updates • BIOS Features • VGA Compatible BIOS • PCI Bus Support • PnP Support • VESA VBE 2.0 (incl.
• Panel Tables • Voltage Switching • Int 15 Hooks • Monitor Sensing 2.4.3 Introduction / Overview The HiQVideo family of high performance multimedia flat panel/CRT GUI accelerators extend CHIPS' offering of high performance flat panel controllers for full-featured notebooks and sub-notebooks. The HiQVideo family offers 64-bit high performance and new hardware multimedia support features. 2.4.3.1 HiQColor Technology The 65555 integrates CHIPS breakthrough HiQColor technology.
The display system can independently place either RGB or YUV data from anywhere in display memory into an on-screen window which can be any size and located at any pixel boundary (YW data is converted to RGB "on-the-fly" on output). Non-rectangular windows are supported via color keying. The data can be fractionally zoomed on output up to 8x to fit the onscreen window and can be horizontally and vertically interpolated. Interlaced and non-interlaced data are supported in both capture and display systems. 2.
The 64-bit wide memory configurations have double the memory bandwidth of the 32-bit wide configurations. The figure below shows the display memory configurations using and external STN-DD buffer: • Some of the 32-bit configurations allow an additional 256K x 16 device to be used for an external 16-bit wide STN-DD buffer, as shown above. • The 65555 supports both video capture/playback and external STN-DD buffer at the same time 2.4.4 Pin Descriptions 2.4.4.
• Display Memory Interface • Flat Panel Display Interface • CRT Interface Power / Ground and Standby Control • Video Interface; Miscellaneous Pin name in parentheses(... ) indicate alternate functions. 2.4.4.
2.4.4.
2.4.4.4 Pin Functions Table 2-8 65555 Pin Functions Ball Pin Name Type Active Description PCI Bus Interface C1 RST# In Low Reset. This input sets all signals and registers in the chip to a known slate. All outputs from the chip are tri-stated or driven to an inactive state. This pin is ignored during Standby mode (STNDBY# pin low). The remainder of the system (therefore the system bus) may be powered down if desired (all bus output pins are tri-stated in Standby mode).
Table 2-8 Ball 65555 Pin Functions Pin Name Type Active Description L4 DEVSEL# S/TS Low Device Select. Indicates the current target has decoded its address as the target of the current access L2 PERR# S/TS Low Parity Error. This signal reports data parity errors (except for Special Cycles where SERR# is used). The PERR# pin is Sustained Tri-state.
Table 2-8 65555 Pin Functions Ball Pin Name Type Active Description U2 T3 R4 T2 U1 R3 T1 R2 R1 P2 N3 P1 N2 M4 M3 N1 J1 J2 H1 J3 J4 H2 G1 H3 G3 F2 E1 F3 D1 E2 F4 E3 P3 M2 K3 F1 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O High High High High High High High High High Hig
Table 2-8 65555 Pin Functions Ball Pin Name Display Memory Interface AA0 (CFG0) D18 AAI (CFG1) Cl9 AA2 (CFG2) B20 AA3 (CFG3) C18 AA4 (CFG4) A20 AA5 (CFG5) Bl9 AA6 (CFG6) Al9 AA7 (CFG7) B18 AA8 (CFG8) C17 AA9 (CFG9) D16 D10 A10 B10 C10 A9 B9 A8 C9 B8 A7 C8 B7 A6 C7 B6 A5 D15 B16 A17 C15 A16 B15 C14 A15 B14 C13 A14 B13 D12 C12 A13 B12 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 MB0 MBI MB2 MB3 MB4 MB5 MB6 MB7 MB8 MB9 MB10 MB11 MB12 MB13 MB14 MB15 (TM0) (TM1) (CFG10) (CFG11) (CF
Table 2-8 Ball 65555 Pin Functions Pin Name Type Active J18 J17 H19 G20 H18 G19 F20 G18 F19 D20 E19 F17 E18 D19 R20 P19 N18 P20 N19 M17 M18 N20 M19 M20 L18 L19 L20 L17 K17 K20 C11 K18# MC0 MC1 MC2 MC3 MC4 MC5 MC6 MC7 MC8 MC11 MC12 MC13 MC14 MC15 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11(RMA16) MD12(rma17) MD13 MD14 MD15 RAS0# PAS1# I/0 l/O l/O l/O l/O l/O l/O l/O l/O I/0 l/O l/O l/O l/O I/0 l/O l/O l/O l/O l/O l/O l/O l/O I/0 l/O l/O l/O l/O l/O l/O Out Out High High High High High High High
Table 2-8 Ball 65555 Pin Functions Pin Name Flat Panel Display Interface P0 W6 P1 V7 P2 Y6 P3 W7 P4 V8 P5 Y7 P6 W8 P7 U9 P8 V9 P9 Y8 P10 W9 P11 Y9 P12 V10 P13 W10 P14 Y10 P15 U10 P16 U11 P17 Y11 P18 W11 P19 V11 P20 Y12 P21 Y13 P22 V12 P23 U12 P24 W13 P25 Y14 P26 V13 P27 W14 P28 Y15 P29 V14 P30 W15 P31 Y16 P32 V15 P33 Y17 P34 W16 P35 U15 Y5 SHFCLK W5 FLM Type Active Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out
Table 2-8 Ball Note: 2-72 65555 Pin Functions Pin Name Type Active Description All signals listed above are powered by DVCC and GND.
Notes for table below: • To accommodate a wide variety of panel types, the graphics controller has been designed to output its data in any of a number of formats. These formats include different data widths for the colors belonging to each pixel, and the ability to accommodate different pixel data transfer timing requirements. • For STN-DD panels, pins PO through P35 are organized into groups corresponding to the upper and lower parts of the panel.
Table 2-8 65555 Pin Functions (continued) Ball Pin Name Type Active Description CRT Interface U3 HYSNC(CSYNC) Out Both CRT Horizontal Sync (polarity is programmable) or "Composite Sync" for support of various external NTSC/PAL encoder chips V2 VSYNC Out Both CRT Vertical Sync (polarity is programmable) Y3 V4 W3 RED GREEN BLUE Out Out Out Analog Analog Analog W2 RSET In N/A Set point resistor for the internal color palette DAC.
Table 2-8 65555 Pin Functions (continued) Ball Pin Name Type Active Description P4, U14, U7, J9-12 K9-12 L9-12 M9-12 Y1 RGND GND H4,N4 BVCC VCC - Power (Bus Interface), 3.3V U8 DVCC VCC - Power (Flat Panel Interface), 3.3V D13 H17 N17 MVCC VCC - Power (Memory Interface), 3.3V. U13 VVCC VCC - Power (Video Interface), 3.3V. Internal reference GND, should be tied to GND Video Interface V16 VREF I/O High Vertical reference input for video data port.
Table 2-8 65555 Pin Functions (continued) Ball Pin Name Type Active Description B1 TD1(MCLKIN) In High Test data input for boundary scan. Can be configured to be used as an input for an externally provided MCLK through a strapping option and register programming. See the descriptions for registers XR70 and XRCF for complete details C2 TDO In High Test data out for boundary scan. D3 TRST# In High Test reset for boundary scan.
2.5 M38813 2.5.1 Overview The M38813M4-XXXHP is an 8-bit single-chip microcomputer created in a silicon gate CMOS process. Built into this single-chip microcomputer are: • Serial l/O function (either clock synchronous or UART method selectable in software) • 8-bit timers • 8-bit Comparator • Double Bus interface The M38813M4-XXXHP is designed as a dedicated microcomputer for Keyboard controller.
Table 2-9 M38813M4-XXXHP Functions Parameter Function Output current Operating temperature range -20 to 85°C Device structure CMOS silicon gate Package M38813M4-XXXHP 2.5.3 10mA (15mA for P24-P27) 64-pin plastic molded QFP (0.5mmlead pitch) Pin Configuration The Pin configuration of the M38813M4-XXXHP is shown in below.
2.5.4 Pin Descriptions The pin functions are listed in the table below. Table 2-10 Pin M38813M4-XXXHP Pin Description Name Function Vcc, Vss Power supply Power supply inputs 2.7 to 5.5V to Vcc, and 0V to Vss. CNVss CNVss Controls the operating mode of the chip. Normally connected to Vss or Vcc. RESET Reset input To enter the reset state, this pin must be kept "L" for more than 2µs (under normal Vcc conditions).
2.5.4.
2.6 YMF715B-S YMF715-S (OPL3-SA3) is a single audio chip that integrates OPL3 and its DAC, 16 bit Sigma-delta CODEC, MPU401 MIDI interface, joystick with timer, and a 3D enhanced controller including all the analog components which is suitable for multi-media application. This LSI is fully compliant with Plug and Play ISA 1.0a, and supports all the necessary features, i.e. 16 bit address decode, more IRQs and DMAs in compliance with PC'96. This LSI also supports the expandability, i.e.
2.6.
2.6.
Table 2-11 YMF715 Descriptions Pin name Pins MP9-0 l0 I/O I+/O Type Size TTL 4mA Function Refer to “multi-purpose pins” section Others: 27 pins GPO - GP3 4 IA - - Game Port GP4- GP7 4 I+ Schmitt 2mA Game Port RXD 1 I+ Schmitt 2rnA MIDI Data Receive TXD 1 O TTL 4mA MIDI Data Transfer /VOLUP 1 I+ Schmitt 2mA Hardware Volume (Up) /VOLDW l I+ Schmitt 2mA Hardware Volume (Down) X331 1 I CMOS 2mA 33.8688 MHz X33O 1 O CMOS 2mA 33.
C h a p t e r 3 BIOS Setup Information The Setup Utility is a hardware configuration program built into your computer’s BIOS (Basic Input/Ouput System). Your computer is already properly configured and optimized, and you do not need to run this utility. However, if you encounter configuration problems, you may need to run Setup. Please also refer to Appendix E, BIOS Post Checkpoints when a problem arises.
Pressing F2 brings up the main screen of the Setup Utility. SETUP Utility Basic System Settings Startup Configuration Onboard Devices Configuration System Security Power Management Load Default Settings ↑ ↓ → ← =Move Highlight Bar, ↵ =Select, Esc=Exit Press the cursor keys (↑ ↑ ↓ → ← ) to move the highlight bar, then press Enter to make a menu selection.
3.1 Basic System Settings The Basic System Settings screen contains parameter items involving basic computer settings. Basic System Settings Date ------------------------------------ [Fri Feb 14, 1997] Time ----------------------------------- [10:00:00] Floppy Disk A ---------------------- [1.44 MB 3.
3.2 Startup Configuration The Startup Configuration screen contains parameter items that are set-up when the computer starts up.
Table 3-2 Startup Configuration Parameters Parameter Operating System Description Selects the operating system the computer is running. Set this parameter to the appropriate OS to get maximum performance. USB Function Support Selects support for USB (Universal Serial Bus). Enable this parameter if you are connecting USB device(s) to the computer.
3.3 Onboard Devices Configuration The Onboard Devices Configuration screen contains parameter items that are related to port devices on your computer.
Table 3-3 Onboard Devices Configuration Parameters Parameter DMA Description Setting Sets the DMA (direct memory access) channel of the infrared port 3 1 Enables or disables the internal modem Enabled Disabled Base Address Sets the I/O base address of the internal modem 3E8h 3F8h 2F8h 2E8h IRQ Sets the IRQ channel of the internal modem 11 5 3 4 10 Enables or disables the parallel port Enabled Disabled Base Address Sets the I/O base address of the parallel port 378h 278h 3BCh IRQ Sets th
3.4 System Security The System Security screen contains parameter items that help safeguard and protect your computer from unauthorized use.
3.5 Power Management Settings The Power Management Settings screen contains parameter items related to power-saving and power management.
Table 3-5 Power Management Settings Parameters Parameter Description Setting or Format Modem Ring Resume On Indicator When enabled, and an incoming modem ring is detected, the computer wakes up from standby mode. When the computer is off or in hibernation mode, the computer will not resume on a modem ring. Enabled Disabled Battery-low Warning Beep Enables or disables warning beeps during a battery-low condition.
3.6 Load Default Settings When you select the Load Default Settings item from the main screen, a dialog box appears asking you to confirm that you want to reset all settings to their factory defaults. Load Setup Default Settings Are you sure? [Yes] [No] Choose Yes to confirm or No if otherwise.
C h a p t e r 4 Disassembly and Unit Replacement This chapter contains step-by-step procedures on how to disassemble the notebook computer for maintenance and troubleshooting. To disassemble the computer, you need the following tools: • Wrist grounding strap and conductive mat for preventing electrostatic discharge • Flat-bladed screwdriver • Phillips screwdriver • Hexagonal screwdriver • Tweezers • Plastic stick The screws for the different components vary in size.
Figure 4-1 Removing the Battery Pack Removing all power sources from the system prevents accidental short circuit during the disassembly process.
4.1.2 Connector Types There are two kinds of connectors on the main board: • Connectors with no locks Unplug the cable by simply pulling out the cable from the connector. • Connectors with locks You can use a plastic stick to lock and unlock connectors with locks. The cables used here are special FPC (flexible printed-circuit) cables, which are more delicate than normal plastic-enclosed cables. Therefore, to prevent damage, make sure that you unlock the connectors before pulling out the cables.
4.1.3 Disassembly Sequence The disassembly procedure described in this manual is divided into four major sections: • Section 4.2: Installing memory • Section 4.3: Removing the modem board • Section 4.4: Removing the hard disk drive • Section 4.5: Removing the keyboard • Section 4.6: Disassembling the inside frame assembly • Section 4.7: Disassembling the display The following table lists the components that need to be removed during servicing.
Ax3 Remove HDD Cover Open Dimm Door Open Battery Door Modem Module DIMM Battery Remove Display Hinge Unplug K/B conector HDD Remove K/B Remove LED Cover Bx2 Remove LED Cover Unplug Inverter Cable Bx1 Cx4 Remove Heat Sink CPU Heat Sink Display Module Ex4 Dx8 Gx2 Unplug Cables Dx4 Release Latches Lower Case Display Bazel Ix2 Upper Case CPU Board Fx3 DC-DC Covert Bd Touch Pad Remove FDD/CD-ROM Inverter Board LCD Pannel Ix3 Jx1 Ix4 Audio Board Keyboard Board Speaker M/B Bx2
4.2 Installing Memory Follow these steps to insert memory modules: 1. Turn off the computer. Then turn the computer over to access its base. 2. Remove three screws from the memory door; then lift up and remove the memory door. Figure 4-4 Removing the Memory Door 3. Remove the memory modules from its shipping container. 4. Align the connector edge of the memory module with the key in the connector. Insert the edge of the memory module board into the connector.
Figure 4-5 5. Installing and Removing Memory Replace the memory door and secure it with the screws. Sleep Manager must be run after installing additional memory for the computer to hibernate properly. If Sleep Manager is active, it will automatically adjust the hibernation file on your notebook. If you are using an operating system other than Windows 95 or DOS, you may need to re-partition your hard disk drive to allow for the additional memory. Check with your system administrator.
4.3 Removing the Modem Board When you open the memory door, you can also access and replace the modem board. See figure below.
4.4 Removing the Hard Disk Drive Follow these steps to remove the hard disk drive: 1. Turn the computer over and locate the hard disk drive bay cover. 2. Press the hard disk drive bay cover release and slide the cover out to remove it. Set aside the cover. 3. Pull the hard disk drive tab to remove the hard disk drive from the hard disk drive bay. Figure 4-7 4. Removing the Hard Disk Drive Store the hard disk drive in an antistatic bag.
4.5 Removing the Keyboard Follow these steps to remove the keyboard: 1. Slide out the two display hinge covers on both sides of the notebook. Figure 4-8 2. Using a pointed instrument, unlock the keyboard locks. keyboard to expose the keyboard connectors.
3. Unplug the keyboard connectors (CN3 and CN5) from the keyboard/touchpad board. Set aside the keyboard.
4.6 Disassembling the Inside Frame Assembly This section discusses how to disassemble the housing, and during its course, includes removing and replacing of certain major components like the internal drive (CD-ROM or floppy), CPU and the main board. Follow these steps: 4.6.1 Removing the Heat Sink Assembly Follow these steps to remove the heat sink assembly: 1. Pull up and remove the LED cover. Figure 4-11 2. Remove the five screws that secure the heat sink assembly to the housing.
4.6.2 Removing the Display Follow these steps to remove the display: 1. Remove two screws on the bottom and two screws on the rear of the unit. Figure 4-13 2. Unplugging the Display Cable Open the display and remove two screws; then pull up the display cable (CN9) and unplug the inverter cable (CN8).
3. Detach the display from the main unit and set aside. Figure 4-15 4.6.3 Removing the Display Hinge Screws Removing the Internal Drive Follow these steps to remove the internal drive: 1. Pull up the FDD/CD module latches. 2. Unplug the two internal drive cables (CN17 for FDD; CN17 and CN20 for CD-ROM). 3. Pull out the internal drive and set it aside. Ensure the drive cables do not become hooked on the inside frame assembly when removing and reinstalling the drive.
Figure 4-16 4.6.4 Removing the Internal Drive Replacing the CPU Gently pull out the CPU heat sink and the CPU board (CN21) from the mainboard. Figure 4-17 Replacing the CPU Reverse the steps above to insert a replacement CPU.
4.6.5 Detaching the Top Cover Follow these steps to detach the top cover from the bottom cover: 1. Unplug the touchpad cable (CN6) from the keyboard/touchpad board, and the audio board cable (CN14), speaker cables (CN13 and CN15) and optionally, the fan connector found just above the speaker cables (CN12) from the mainboard. Figure 4-18 2. Detach the top cover from the bottom cover.
4.6.6 Removing the Mainboard Follow these steps to remove the mainboard: 1. Remove the screws found on the lower case (ten total screws, two screws shorter than the rest found on the front corners of the computer). Figure 4-20 2. Removing the Bottom Screws Remove the keyboard/touchpad board (CN18). Remove two screws and remove the plate that covers the DC-DC converter board.
3. Gently remove the DC-DC converter board (CN7). Figure 4-22 4. Unplug the battery charger connector (CN22) and remove four screws that secure the motherboard to the base assembly. Then pull up to remove the mainboard.
4.6.7 Disassembling the Mainboard Follow these steps to disassemble the mainboard: REMOVING THE CHARGER BOARD Unplug the charger board (containing the power switch, DC-in jack and PS/2 port). Figure 4-24 Removing the Charger Board REMOVING THE PCMCIA SOCKETS The PC Card Connector Module is normally part of the motherboard spare part. The following removal procedure is for reference only.
4.6.8 Disassembling the Top Cover The touchpad, speakers, audio board are connected to the top cover. The sections below describe the removal process of these components. REMOVING THE HARD DISK DRIVE HEAT SINK Pull up to remove the hard disk drive heat sink from the top cover. Figure 4-26 Removing the Hard Disk Drive Heat Sink REMOVING THE AUDIO BOARD Pull up to remove the audio board from the top cover.
REMOVING THE TOUCHPAD 1. Remove four screws and lift up the metal plate and touchpad buttons. 2. Unplug the touchpad cable (J1) and remove the touchpad main sensor and connector unit. REMOVING THE SPEAKERS 1. Unlock the speaker by pushing outward on its locks. 2. The flip up the wire that holds the speaker in place and remove the speaker.
4.7 Disassembling the Display Follow these steps to disassemble the display: 1. Remove the two oval LCD bumpers at the top of the display; use a pointed instrument to remove the two mylar stickers on the bottom of the display. Figure 4-29 2. Removing the LCD Bumpers Remove four screws on the display bezel. Figure 4-30 Removing the Display Bezel Screws STN and TFT LCDs use the same bezel but different panels.
3. Pull out and remove the display bezel by first pulling on the inside of the bezel sides and lower bezel area. Then pull up the top bezel area. Figure 4-31 4. Removing the Display Bezel Unplug two connectors and remove the inverter board.
5. Remove three screws on the four sides of the display panel (one screw holds and grounds the LCD cable). Then tilt the LCD Panel away for the display cover.
A p p e n d i x A Model Number Definition This appendix shows the model number definition of the notebook. 390XX - X X X X Brand T: TI Keyboard Language Versions: 0: Swiss/US 1: US(110V) 2: US(220V) 3: US w/o power cord 4: US K/B w/o power cord(ACLA) 5: US(110V for AAB) 6: US(220V)with CCIB for P.R.
A p p e n d i x Exploded View Diagram This appendix includes exploded view diagrams of the notebook. Table B-1 Exploded View Diagram List No.
A p p e n d i x C Spare Parts List This appendix lists the spare parts of the notebook computer. Table C-1 Category Spare Parts List Ref. No. of Exploded Diagram Description Acer Part No. Comment/Location Min. Qty LCD Module B-4 INVERTER BD 19.21030.111 (HIT TFT) E-2/3 LCD PANEL LATCH PACK 6M.43A06.001 34.47604.001 SPRING * 4 + 42.43A01.001 LACTCH*2 5 5 B-3 C.A 41/50P IBM12.1 TFT 170MM 50.43A01.011 LCD TO MB CABLE 20 B-10 W.A 10P #30 220MM INVERTER 390 50.43A02.
Table C-1 Category Lower Case Spare Parts List Ref. No. of Exploded Diagram D-10 ~ D-13 Description Acer Part No. Comment/Location PCMCIA DOOR PACK 390 6M.43A07.001 INCLUDING THE FOLLOWING PARTS D-10 34.43A12.001 SPRING PCM DOOR UPPER SUS 390 * 4PCS D-11 34.46928.001 SPRING PCM DOOR_L SUS PEACH * 4 PCS D-12 42.46913.001 DOOR PCMCIA ABS 050 370 *2PCS D-13 42.46919.001 DOOR(L) PCMCIA ABS 050 AN370 * 2PCS Min. Qty 5 ASSY LOWER CASE 050 390 60.43A07.001 1 IC CHARGER T62.069 05.62069.
Table C-1 Category Spare Parts List Ref. No. of Exploded Diagram Memory Acer Part No. Comment/Location Min. Qty DIMM EDO 16MB 3.3V 60NS 55.46804.011 1 DIMM EDO 32MB 3.3V 60NS 4K 55.46804.021 1 DIMM EDO 32MB 3.3V 60NS 55.46804.031 1 KAS1901-0184R 050 SWISS 90.46907.000 1 KB-84 KEY KAS1901-0161R US 370 90.46907.001 1 KAS 1901-0-0166R 050 US/A 90.46907.005 1 KAS 1901-0167R 050 ARABIA 90.46907.00A 1 GER KEYBD 9805758-0003 PEACH 90.46907.00G 1 KAS1901-0162R 050 HEB 90.46907.
Table C-1 Category Touchpad Spare Parts List Ref. No. of Exploded Diagram Description Acer Part No. INTERNAL CD-ROM DRIVE KIT 390 91.43A28.003 PLT FOR COVER SW(TOOL) 390 31.43A05.001 BRACKET T/P SUS N/A 390 33.43A05.001 KNOB TOUCH PAD (TOOLING) 390 42.43A10.001 C.A 8P FPC TOUCHPAD 390 50.43A03.001 Comment/Location Min. Qty 1 IN BRACKET 50 50 50 TOUCHPAD CABLE 5 TOUCHPAD SYNA/TM3202TPD-226 50 56.17447.061 5 Adapter ADT 90-264V ADP-45GB V.E3 370P 25.10046.
A p p e n d i x Schematics This appendix shows the schematic diagrams of the notebook. Table D-1 Schematics List No.
+2.9V 1 C379 C352 2 ST100U10VDM SCD1U C351 C361 SCD1U SC1KP C360 C355 C354 SC1KP SCD1U SC1KP CPU BD TO BD CONNECTOR +3.3v +5V +2.
5 $MKR# +5V +5V C194 SC1KP C198 SCD1U C203 SC2D2U16V5ZY C195 SCD1U NEAR R7,P6,G6 PIN 1,5 $CPUD[0..63] +3.3V C200 SC1KP C192 SCD1U C190 SC2D2U16V5ZY NEAR R14,F6 PIN +3.3V C193 SC1KP C197 SCD1U C189 SC2D2U16V5ZY NEAR R15,P15,G15 F15,F14 PIN L2 SIZE IO_VOLTAGE 1 1 R175 10KR3 2 R173 10KR3 2 $CPUA22 L2 BANK $CPUA21 L2 TYPE IO_VOLTAGE IO_VOLTAGE 1 1 R176 10KR3 2 R172 10KR3 2 $CPUA24 1,5 $CPUA23 $BE#[0..
15 FDD/PRT# 4 SPLED SPLED 4,8,23 2 9 ENAVEE CCFT 4 DISPLAY 21 $RI 22 BL1# 22 BL2# 22 BAT_USE# 13 HOTKEY# 22 PWRGOOD SETUP# 12 SYS_COM GPI9 15 GPI9 4 CARD $SLOWDWN SYSCLK EJECT 23 DOCK_IN_SMI# 2,5,9,11,12 2,9,11 $PCIRST# $AD[0..31] 4,10 ID_CLK 4,10 13 ID_DATA IO10 CHGR_DATA IO11 CHGR_CLK 13 20 CD/FDD# SDRAM 7 16 FIR_EN# 1 CPU_COM 13 COVERSW 13 HOTKEY1 $CBE#[0..3] 2,9,11 +3.
M1533 BYPASS CAPACITORS 1 3 SMEMW# +5v R116 2 3,11,14,17,21 3,11,14,21 3,11,14,17,21 DUMMY-R3 1 C171 2 ST4D7U +5V C173 SC1KP 3 N0WS# IOCHK# REFSH# SBHE# 3,21 3 3,21 Near pin [R7] 1 2 3 4 5 +5V IRQ3 IRQ4 IRQ5 IRQ6 IRQ3 IRQ4 IRQ5 IRQ6 3,14 RP67 1 2 3 4 SRN10K 3 SMEMR# RP69 10 9 8 7 6 M16# 3 8 7 6 5 1 3 $AMSTAT# R110 2 DUMMY-R3 SRP10K 3 SYSCLK +5V +5V USE C161 SCD1U 3,14 3,14 3,14 1 2 3 4 5 DACK#5 DACK#6 DACK#7 +5V DACK#5 DACK#6 DACK#7 CLOSE TO PIN [P6] RP18 10 9 8 7 6
256K L2 PIPELINE BURST CACHE +5V +5V $CPUD[0..63] 1,2 $$$$ $$$$$$$ $$$ $$$$$$$ $$$$ $ CCCCCCCCCCCCCCCCCCCCCCCCCC PPPP PPPPPPP PPP PPPPPPP PPPP P UUUUUUUUUUUUUUUUUUUUUUUUUU DDDDDDDDDDDDDDDDDDDDDDDDDD 0123 4567891 111 1111112 2222 2 0 123 4567890 1234 5 +3.
+3.3V C392 C394 SC4D7U16V6ZY SCD1U 2,7 C397 SCD1U $MD[0..63] C398 SCD1U C391 SC4D7U16V6ZY C390 C399 C393 C396 C395 SC4D7U16V6ZY SCD1U SCD1U SCD1U SCD1U $MD[0..63] CN26 2 $CAS#[0..7] $MCAS#[0..7] RP39 $CAS#01 $CAS#12 $CAS#23 $CAS#34 8 7 6 5 SRN10 RP37 8 7 6 5 SRN10 $CAS#41 $CAS#52 $CAS#63 $CAS#74 $MCAS#4 $MCAS#5 $MCAS#6 $MCAS#7 8 7 6 5 SRN10 $MA12 $MA13 2 $A[2..11] $MAA0 7 $MAA1 7 8 $SDRAM_CLK0 $MA[2..
+3.3V C380 C388 SC4D7U16V6ZY SCD1U 2,6 C385 SCD1U C386 SCD1U C381 SC4D7U16V6ZY C382 C387 C384 C389 C383 SC4D7U16V6ZY SCD1U SCD1U SCD1U SCD1U $MD[0..63] $MD[0..63] CN25 $MCAS#[0..7] $MA[2..
1 R310 2 33R3 UY1 9,23 1 2 3 $VGA14M +3.3V 1 VCC 5 BE# 4 NC7SZ384-2 3 TV_EN R265 22R3 2 C330 SCD1U 1 4 4 SCD1U R312 1 2 33R3 5 +5V CY1 SCD1U 1 RZ6 2 10KR3 3 QZ1 2N7002 2 1 U38B 1 6 7 1 4 1 2 SSAHCT125 U38A 1 1 3 7 SSAHCT125 1 +5V R271 2 33R3 R102 2 33R3 R272 2 33R3 R257 2 33R3 R256 2 33R3 M O D E M 1 4 M 1 MODEM14M21 G14.318M 3 C174 SCD1U C331 C343 C178 SCD1U SCD1U SCD1U C336XTAL-14.
$VAA8 $VAA7 $VAA6 $VAA5 1 2 3 4 $VAA4 $VAA3 $VAA2 $VAA1 1 2 3 4 $VAA0 RP6 SRN33 RP9 1 +3.3V 8 7 6 5 SRN33 R88 C62 SCD1U 8 7 6 5 2 33R3 2,3,11 2,3,11 2,3,11 2,3,11 2,3,11 2,3,11 $AD22 RNZ2 SRN33 8 7 6 5 $FRAME# 1 $IRDY# 2 $TRDY# 3 $DEVSEL# 4 $STOP# $PAR $CBE#[0..3] 2,3,11 R48 1 $CBE#0 $CBE#1 $CBE#2 $CBE#3 +3.3V C109 SC1KP C103 SCD1U 3 $PCIRST# 8 $VGACLK 8 $VGA14M C92 SCD1U 2,11 3 1 $SERR# $PERR# $AD[0..31] +3.
+5V 1 DOCK_HSYNC 23 $DOCK_B 23 DOCK_VSYNC 23 DOCK_VSW3 23 DOCK_DDC_CLK23 R199 15KR3 2 R206 2 100R3 C26 SC47P R203 1 2 4 VSW3 1KR3 C234 SC47P R200 VSYNC 1 2 9 VSYNC 10R3 C235 SC47P L2 $BLUE 1 2 9 $BLUE NL322522T-2R2 1 R19 2 C247 SC47P 75R3 CRT_GND R202 HSYNC 1 2 CRT_GND 9 HSYNC 10R3 C236 SC47P L3 NL322522T-2R2 2 9 $GREEN $GREEN 1 C261 1 R28 2 SC47P R18 75R3 CRT_GND CRT_GND 1 100R32 9 DDC_DATA R8 C245 2 +5V 1 L1 SC47P 15KR3 NL322522T-2R2 2 9 $RED $RED 1 C237 R9 1 2 SC47P 75R3 R3 CRT_GND CRT_GND 1 1KR32 4
12 ACCLK 12 ACCBE#[0..3] 12 ACAD[0..
A_SLOT_VCC B_SLOT_VCC 1 1 C117 C116 C118 C319 SCD1U SCD1U SCD1U SCD1U 2 2 C306 C305 ST10U16VBMST10U16VBM +3.3V +5V C127 SCD1U C126 SCD1U C119 C128 SCD1U SC22U10V0ZY +12V C140 SCD1U C139 SCD1U 1 C145 C321 SCD1U 2 ST22U A_VPP C138 SCD1U C107 SCD1U C122 SCD1U C302 SC2D2U50V ACAD0 11 ACCD1# ACAD1 ACAD2 ACAD3 ACAD4 ACAD5 ACAD6 ACAD7 +3.3V +5V +12V 3 $PCIRST# 11 $DATA 11 $CLOCK 11 $LATCH 15 16 17 1 2 30 7 24 U31 3.3V 3.3V 3.
CHGR_5VSB C277 SCD1U +5V KKK KKK KK KKK KKK KK CCCCCCCCCCCCCCCC OOOOOOOOOOOOOOOO LLL LLL LL LLL LLL LL 123 456 78 911 111 11 01 234 56 C146 SCD1U KROW8 KROW7 KROW6 KROW5 KROW4 KROW3 KROW2 KROW1 TDATA TCLK XD7 XD6 XD5 XD4 XD3 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 4 84 74 64 54 44 34 24 14 03 93 83 73 63 53 43 3 P P P P P P P P P P P P P P P 01 02 03 04 05 06 07 00 11 12 13 14 15 16 1P 1 0 7 XD[0..
+5V PLACE BYPASS CAPS COLSE TO IC'S C27 SCD1U 4,17 DACK#[1..
+5V 1 14,23 RP1 PPD4 1 PPD5 2 PPD6 3 PPD7 4 5 PRT+5V R5 SRP4K7 PBUSY 1 2 1KR3 PPD[0..
+5V +5V +5V 1 4 1 0 9 1 CPU_COM 12 SYS_COM 1 +5V R321 DUMMY-R3 1 2 1 2 3 4 C3 SCD1U C233 ST10U16VBM 1 U14 GND OUT 8 IN OUT 7 IN OUT 6 EN# OC# 5 TPS2014 R208 100KR3 1 C24 2 ST100U10VDM 1 C249 SCD1U RX22 2 1 2 10KR3 1 +3.
+5V +5VA PIN 3 VDDA 1 C34 2 ST4D7U C83 SC1KP PIN 57 C278 SC1U25V5MY C57 SCD1U C73 SC1KP PIN 80 VDDD C293 SCD1U +5VA C292 SCD1U C256 +6V SCD1U C101 R69 1 SC1U25V5MY RX23 1KR3 C274 C84 SC1U25V5MY SC1U25V5MY RX24 1KR3 1 CD_AUDL 20 10KR3 C100 SC3300P50V3KX U3 OUT INPUT SENSE FB SD 5V/TAP GND ERROR LP2951ACM 8 7 6 5 C255 SCD1U C254 SCD1U25V5MY 2 R63 1 18 LINE_IN_R C79 2 1 2 3 4 2 CD_AUDR 20 10KR3 C85 SC3300P50V3KX 1 2 18 LINE_IN_L SC1U25V5MY 1 18 RDATA_RACE R64 10K
+5V -INL 1 +5V 2 C290 1 ST4D7U RZ13 10KR3 2 3 ENAUDIO# +OUTL -OUTL -INL 1 17 SOUND_L 1 R80 R85 33KR3 1 2 3 4 5 6 7 8 U27 SH_DOWN GND +OUTA VDD -OUTA -INA GND +INA LM4863 2 -OUTL 47KR3 CZ5 2 C308 2 1 SC150P LINE_OUT_L ST100U10VDM CN13 1 2 CON2-10 -OUTL +OUTL HP-IN GND +OUTB VDD -OUTB -INB BYPASS +INB 16 15 14 13 12 11 10 9 OP_HP_IN +OUTR 1 -OUTR -INR OP_HP_IN 23 CX28 SC1KP R76 100KR3 CX29 SC1KP CN15 1 2 CON2-10 -OUTR +OUTR 2 C291 SC1U25V5MY 1 -INR R77 1 17 SOUND_R R73
+5V 1 +5V R232 1KR3 C282 SCD1U 2 22 PWRGOOD# 3 RTCAS 3 RTCRW 3 RTCDS 3 RTC256 G2 GAP-OPEN 2 2 GY1 GAP-OPEN1 1 BT1 BH-12 2 1 U22 VCC AD7 11 AD6 10 CS# AD5 9 AS R/W# AD4 8 AD3 7 DS RST# AD2 6 RCL# AD1 5 4 EXTRAMAD0 19 BC INT# 23 X1 32K MOT 1 X2 VSS 12 VSS 16 X1 1 2 BQ3285LD XTAL-32.768KHZ 24 13 14 15 17 18 21 22 20 2 3 CX10 SC2P XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 DC_5VSB +3.
+5V L13 1 2 CDROM_5V SCHOKE-D 42 HDD_5V DSD4 1 DSD5 2 DSD6 3 DSD7 4 5 RP25 10 9 8 7 6 DSD0 DSD1 DSD2 DSD3 1 SRP10K HDD_5V R305 5K6R3 2 3 PIDEDRQ 2 3 PIDE_DACK# R306 33R3 DSD121 DSD132 DSD143 DSD154 5 RP55 HDD_5V 10 9 8 7 6 1 DSD8 DSD9 DSD10 DSD11 PIDEA2 IDE_CS3# R307 4K7R3 4 4 +5V L18 1 2 1 SCHOKE-D C342 2 ST22U C344 ST10U16VBM CN19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 2 SRP10K HDD_5V IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D1
XXDIR R338 1 2 DUMMY-R3 R339 DIS_ROM1 SD[0..
R210 2 560R3 1 3 SLEEP# R12 1 2 13 MEDIA_LED# 560R3 1 CHGR_LED# R13 1 2 13 NLLED# 560R3 1 13 CLLED# 1 3 POWER_LED AD+5V R204 2 560R3 R32 2 560R3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 R14 2 560R3 +3.3V +6V 1 C232 1 C61 C252 2 ST100U10VDM 2ST100U10VDM SC1U10V5KX +2.
3 BUFFER_EN 14 PAUTOFD# 14 PERROR# 14,15,23 PPD2 R221 DOCK+5V 1 100R32 3 $STANDBY# 18 OP_HP_IN 18 LINE_OUT_R 18 LINE_IN_R 14 PDCD1# 15 EXT_FDD_SMI# 13 MSCLK 13 KBCLK 10 DOCK_DDC_DATA 10 DOCK_VSYNC 10 $DOCK_B 10 $DOCK_R 22 DC_IN DC_IN 14,15,23 PPD3 14,15,23 PPD4 14,15,23 PPD6 14 PBUSY 14 PSLCT 14 PRI1# 14 PCTS1# 14 PRTS1# 14 PDSR1# 14 WRTPRT# 14 WGATE# R55 14 STEP# 2 3 EXT_FDD_5V_ON 1 DSKCHG# 100R3 14 R43 3 3MODE# 2 DOCK_OK 1 100R3 10 DOCK_DDC_CLK 16 USBPWR1USBPWR1 3,4,16 $USBP00 DOCK_IN2# CN5 1 2 DOCK_IN
A p p e n d i x E BIOS POST Checkpoints This appendix lists the POST checkpoints of the notebook BIOS. Table E-1 POST Checkpoint List Checkpoint Description 04h • Dispatch Shutdown Path Note: At the beginning of POST, port 64 bit 2 (8042 system flag) is read to determine whether this POST is caused by a cold or warm boot. If it is a cold boot, a complete POST is performed. If it is a warm boot, the chip initialization and memory test is eliminated from the POST routine.
Table E-1 POST Checkpoint List Checkpoint Description • KB controller(8041/8042) testing • KB type determination • Write default command byte upon KB type 24h • PIC(8259) testing & initialization 30h • System Shadow RAM 34h • DRAM sizing 3Ch • Initialize interrupt vectors 4Bh • Identify CPU brand and type 35h • PCI pass 0 40h • Assign I/O if device request 41h • Assign Memory if device requested 44h • Assign IRQ if device request 45h • Enable command byte if device is O
Table E-1 POST Checkpoint List Checkpoint Description 80h • Set security status 84h • KB device initialization • Enable KB device 6Ch • 88h • 89h • 90h • Display POST status if necessary 93h • Rehook int1c for quiet boot 94h • Initialize I/O ROM A4h • Initialize security feature A8h • Setup SMI parameters A0h • Initialize Timer counter for DOS use ACh • Enable NMI • Enable parity checking • Set video mode • Power-on password checking • Display configuration tabl
