Datasheet

Datasheet, Volume 1 79
Electrical Specifications
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
IL
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
4. V
IH
and V
OH
may experience excursions above V
DDQ
. However, input signal drivers must comply with the signal quality
specifications.
5. This is the pull down driver resistance.
6. R
VTT_TERM
is the termination on the DIMM and is not controlled by the processor.
7. COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to V
SS
.
Table 7-10. DDR3 Signal Group DC Specifications
Symbol Parameter
Alpha
Group
Min Typ Max Units Notes
1
V
IL
Input Low Voltage (e,f) — — 0.43*V
DDQ
V2,4
V
IH
Input High Voltage (e,f) 0.57*V
DDQ
——V3
V
OL
Output Low Voltage
(c,d,e,f) —
(V
DDQ
/ 2)* (R
ON
/
(R
ON
+R
VTT_TERM
))
—6
V
OH
Output High Voltage
(c,d,e,f) —
V
DDQ
– ((V
DDQ
/ 2)*
(R
ON
/(R
ON
+R
VTT_TERM
))
—V4,6
R
ON
DDR3 Clock Buffer On
Resistance
—21 — 31 5
R
ON
DDR3 Command Buffer On
Resistance
—16 — 24 5
R
ON
DDR3 Control Buffer On
Resistance
—21 — 31 5
R
ON
DDR3 Data Buffer On
Resistance
—21 — 31 5
Data ODT
On-Die Termination for
Data Signals
(d) 93.5 — 126.5 
I
LI
Input Leakage Current — — — ± 500 A
SM_RCOMP0
COMP Resistance (t) 99 100 101  7
SM_RCOMP1
COMP Resistance (t) 24.7 24.9 25.1  7
SM_RCOMP2
COMP Resistance (t) 128.7 130 131.3  7