Datasheet

Datasheet, Volume 1 71
Electrical Specifications
Table 7-3. Signal Groups (Sheet 1 of 2)
1
Signal Group
Alpha
Group
Type Signals
System Reference Clock
Differential (a) CMOS Input
BCLK[0], BCLK#[0],
BCLK[1], BCLK#[1],
PEG_CLK, PEG_CLK#
Differential (b) CMOS Output BCLK_ITP, BCLK_ITP#
DDR3 Reference Clocks
2
Differential (c) DDR3 Output
SA_CK[3:0], SA_CK#[3:0]
SB_CK[3:0], SB_CK#[3:0]
DDR3 Command Signals
2
Single Ended (d) DDR3 Output
SA_RAS#, SB_RAS#,
SA_CAS#, SB_CAS#
SA_WE#, SB_WE#
SA_MA[15:0], SB_MA[15:0]
SA_BS[2:0], SB_BS[2:0]
SA_DM[7:0], SB_DM[7:0]
SM_DRAMRST#
SA_CS#[3:0], SB_CS#[3:0]
SA_ODT[3:0], SB_ODT[3:0]
SA_CKE[3:0], SB_CKE[3:0]
DDR3 Data Signals
2
Single ended (e) DDR3 Bi-directional SA_DQ[63:0], SB_DQ[63:0]
Differential (f) DDR3 Bi-directional
SA_DQS[8:0], SA_DQS#[8:0]
SA_ECC_CB[7:0]
3
SB_DQS[8:0], SB_DQS#[8:0]
SB_ECC_CB[7:0]
3
TAP (ITP/XDP)
Single Ended (g) CMOS Input TCK, TMS, TRST#
Single Ended (ga) CMOS Input TDI, TDI_M
Single Ended (h)
CMOS Open-Drain
Output
TDO, TDO_M
Single Ended (i)
Asynchronous CMOS
Output
TAPPWRGOOD
Control Sideband
Single Ended (ja)
Asynchronous CMOS
Input
VCCPWRGOOD_0,
VCCPWRGOOD_1, VTTPWRGOOD
Single Ended (jb)
Asynchronous CMOS
Input
SM_DRAMPWROK
Single Ended (k) Asynchronous Output RESET_OBS#
Single Ended (l)
Asynchronous GTL
Output
PRDY#, THERMTRIP#
Single Ended (m) Asynchronous GTL Input PREQ#
Single Ended (n) GTL Bi-directional CATERR#, BPM#[7:0]
Single Ended (o)
Asynchronous Bi-
directional
PECI
Single Ended (p)
Asynchronous GTL Bi-
directional
PROCHOT#