Datasheet

6 Datasheet, Volume 1
8-2 Socket Pinmap (Top View, Upper-Right Quadrant) ........................................................86
8-3 Socket Pinmap (Top View, Lower-Left Quadrant) ..........................................................87
8-4 Socket Pinmap (Top View, Lower-Right Quadrant) ........................................................88
Tables
1-1 Related Documents .................................................................................................18
2-1 Supported DIMM Module Configurations .....................................................................20
2-2 DDR3 System Memory Timing Support.......................................................................20
2-3 System Memory Pre-Charge Power Down Support .......................................................23
2-4 Processor Reference Clock Requirements....................................................................33
4-1 Processor Core/Package State Support.......................................................................39
4-2 G, S, and C State Combinations ................................................................................40
4-3 D, S, and C State Combination..................................................................................40
4-4 Coordination of Thread Power States at the Core Level.................................................43
4-5 P_LVLx to MWAIT Conversion....................................................................................43
4-6 Coordination of Core Power States at the Package Level...............................................46
4-7 Targeted Memory State Conditions ............................................................................49
6-1 Signal Description Buffer Types.................................................................................53
6-2 Memory Channel A ..................................................................................................54
6-3 Memory Channel B ..................................................................................................55
6-4 Memory Reference and Compensation........................................................................56
6-5 Reset and Miscellaneous Signals................................................................................56
6-6 PCI Express* Based Interface Signals ........................................................................58
6-7 DMI—Processor to PCH Serial Interface......................................................................58
6-8 PLL Signals.............................................................................................................58
6-9 Intel
®
Flexible Display Interface................................................................................59
6-10 JTAG/ITP................................................................................................................59
6-11 Error and Thermal Protection ....................................................................................60
6-12 Power Sequencing...................................................................................................61
6-13 Processor Core Power Signals ...................................................................................61
6-14 Graphics and Memory Power Signals..........................................................................63
6-15 Ground and NCTF....................................................................................................63
6-16 Processor Internal Pull Up/Pull Down..........................................................................64
7-1 VRD 11.1/11.0 Voltage Identification Definition...........................................................67
7-2 Market Segment Selection Truth Table for MSID[2:0]...................................................70
7-3 Signal Groups 1 ......................................................................................................71
7-4 Processor Absolute Minimum and Maximum Ratings.....................................................73
7-5 Processor Core Active and Idle Mode DC Voltage and Current Specifications....................74
7-6 Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications .....................74
7-7 Processor Graphics VID based (V
AXG
) Supply DC Voltage and Current Specifications.........76
7-8 V
CC
Static and Transient Tolerance ............................................................................76
7-9 V
AXG
Static and Transient Tolerance...........................................................................78
7-10 DDR3 Signal Group DC Specifications.........................................................................79
7-11 Control Sideband and TAP Signal Group DC Specifications.............................................80
7-12 PCI Express* DC Specifications .................................................................................81
7-13 PECI DC Electrical Limits ..........................................................................................82
8-1 Processor Pin List by Pin Name..................................................................................89